Physical Property Regulation Of Molybdenum Disulfide And Development Of Junction Field-Effect Transistors

The short channel effect（SCE）and dielectric tunneling effect seriously restrict the reduction of silicon transistor feature size and become an insurmountable obstacle for the semiconductor manufacturing industry at present.In recent years,transistors with new structures and new principles based on new two-dimensional（2D）semiconductor materials have shown wide application prospects in the field of microelectronics.In addition,with the development of van der Waals（vd Ws）heterogeneous integration technology,it is possible to stack different dimensions and different types of 2D materials,which provides a way to prepare electronic devices based on high-quality vd Ws heterojunction.Notably,studies on graphene nanoribbons（NRs）have shown that 2D quantum confinement can open the graphene energy gap,which is inversely proportional to the width of the NRs.At present,some studies have used this method for reference,first-principles calculations have shown that NRs in MoS₂ systems also exhibit properties different from those of sheet shape.In the actual experimental process,due to the dislocation,lamination,and vacancy defects introduced in the etching process,as well as the edge effects such as hanging bonds at the edge of NRs,it also exhibits semiconducting properties different from those of lamellar materials.In this thesis,we mainly aimed at the low dimensional semiconductor materials MoS₂,as a channel transmission layer,combining the size cutting edge effect is studied in detail the impact of the performance of the transistor,and connecting with the preparation of homogeneous and heterogeneous vd Ws heterogeneous integration technology junction field-effect transistor（JFET）,and explored the logic electronics applications,specific work is as follows:1.Development of MoS₂ NR top-gated transistor based on plasma etching.MoS₂is etched into NRs by plasma dry etching technology,and the top-gated transistor of MoS₂ is prepared on the sapphire insulating substrate as channel material.The channel width of the prepared top-gated transistor is controllable,which is strictly limited by the diameter of the hard mask of the nanowires.The 150 nm short channel device exhibits a driving current up to 496μA/μm,the switching ratio can reach 10⁷,the threshold voltage is less than 3 V,and the mobility is more than 50 cm²V^-1s^-1.At the same time,the effect of different thicknesses of MoS₂ NRs on the performance of transistors is studied.When the thickness of MoS₂ NRs is high enough,the transistors form a fin-like field-effect transistor（Fin FET）structure.Benefit by the high electrostatic coupling of the grid in this structure,the control capability of the gate is greatly enhanced,which is verified by COMSOL multi-electric field coupling simulation.Finally,based on the excellent switching and current saturation characteristics of MoS₂ NR top-gate transistors,we assembled an inverter and a NAND gate on a single MoS₂ NR,which provided a voltage gain of-17.8 and a relatively ideal noise tolerance.Under the background that silicon-based electronic devices have reached the physical limit,this research work provides a new preparation method for the research and development of the next generation of electronic devices.2.The doping technology of silicon-based semiconductors will inevitably be affected by the random doping effects with the continuous reduction of transistor size.However,low-dimensional semiconductor materials can be precisely modulated by sizing without the need for complex and random doping processes.In this paper,by using vd Ws heterogeneous integration technology and dry physical transfer process to transfer MoS₂ flakes with thickness greater than 50 nm above plasma etched MoS₂ NRs to construct MoS₂ homojunction with mutation level.Based on the rectifying characteristics of homojunction up to 10⁴,we constructed a homojunction FET based on size tailoring based on MoS₂ NR as the channel and Bulk-MoS₂ as the gate,which verified that transverse size restriction and edge effect can effectively modulate the physical properties.The device exhibits negligible gate lag,subthreshold swing（SS）as low as 120 mV·dec^-1,and robust gate regulation with saturation current density as high as 46μA·μm^-1.Finally,we perform a basic logic function verification against the transistor,and the inverter presents a voltage gain of up to-15.4 and a power supply voltage noise tolerance of 83%.This work is compatible with existing Si-based technologies,and the proposed research strategy opens up new possibilities for manufacturing transistors based on derivatives of the same materials.3.Development of heterojunction FET based on MoS₂.A heterojunction FET based on MoS₂/β-Ga₂O₃ is constructed on Si O₂/Si substrate by reasonable band structure design.MoS₂ obtained by mechanical stripping was used as the channel,andβ-Ga₂O₃ obtained by mechanical stripping was used as the gate.The transistor has a switching ratio of 10⁸ and a SS as low as 69 m V·dec^-1.Independent dual-gate regulation is achieved under the influence of back-gate induction.Finally,we construct the inverter,“NAND”gate,and“OR”gate,and verify the actual logic function.The inverter assembled by MoS₂/β-Ga₂O₃JFET has a voltage gain of-28 and a near-ideal noise tolerance of 90.4%.This work not only provides an efficient heterogeneous integration strategy for implementing high-performance FET but also provides an effective method for designing high-performance logic electronic devices by adjusting threshold voltage with dual gate control.