Study On Tracking Trigger Algorithm And FPGA Acceleration For STCF Main Drift Chamber

Super Tau Charm Facility(STCF),the new generation of electron-positron collider proposed by Chinese scientists,started its pre-research work in 2018,and the conceptual design is currently underway.STCF will play an important role in frontier major topics such as exploring the asymmetry of matter and antimatter in the universe(CP violation),studying of the internal structure of hadrons and the nature of non-perturbative strong interactions,searching for exotic matter and new physical phenomena beyond the standard model.STCF can be designed to span the center-of-mass energies ranging from 2.0 to 7.0 GeV with a peak luminosity greater than 0.5×1035cm-2s-1,which is two orders higher than Beijing Electron-Positron Collider Ⅱ’s(BEPCⅡ’s).Main Drift Chamber(MDC),serves as the central tracker STCF detection spectrometer and its task is to measure and reconstruct charged tracks together with the inner tracker.MDC also provides information on tracks of charged particles to trigger system.STCF reaches the maxing event rate of 400 kHz when it is operated at the peak luminosity at(?)＝4 GeV.The high luminosity brings a rise in false trigger rate under high background.The data size of detector system also increases under high event rate.Facing with a complex background environment,if the trigger system can obtain the track parameters of charged particles in the main drift chamber,it can suppress the background by matching the tracks with other sub-detectors more precisely and reduce the false trigger rate.The range of data read by the data acquisition system from the front-end electronics is determined by the detector readout time and the timing accuracy of the trigger signal.Reconstructing the event start time in the level-1 trigger can reduce the trigger readout range and compress the event size.The MDC sub-trigger in the firstlevel trigger carries tracing,reconstructing the track on the r-φ plane,and reconstructing the particle hit time to assist the reconstruction of the event start time.The bandwidth of detector data readout increases under high event rate,and the buffer capacity of front-end electronics is limited.The STCF project team hopes to control the MDC sub-trigger delay within 1 μs.The complex triggering functions including charged particle tracking,track reconstruction on the r-φ plane and reconstruction of the particle hit time of the main drift chamber within 1μs delay bring a huge challenge to STCF MDC sub-trigger algorithm design and trigger logic implementation.Field Programmable Gate Array(FPGA)has a large number of high-performance combinational logic and flip-flops,memory resources,and numerous high-speed data input and output(IO)interfaces.It also has strong flexibility and short development cycle.FPGA has been widely used in triggering systems of large-scale particle physics experiments.Advanced FPGA chip also integrates many digital signal processors(DSPs),which is more conducive to high-speed parallel processing of complex data flows.This is an ideal choice for deploying low-latency track triggering algorithms.Based on these advantages,this paper proposes to use FPGA as a hardware platform to complete tasks such as tracking and r-φ plane track reconstruction in the sub-trigger of STCF MDC,and to realize the reconstruction of particle impact time to assist in the reconstruction of case starting time.This paper carries out research on the above-mentioned track triggering algorithm,and on this basis explores the FPGA implementation and computing acceleration of the core algorithm.The contents of this paper are as follows:(1)Track reconstruction algorithm based on two-level pattern matching:Through the investigation of the currently running high luminosity collider experiments,the realtime track reconstruction algorithms suitable for STCF MDC sub-trigger include pattern matching and Hough transform.Compared with the Hough transform,the advantage of pattern matching is low computational complexity,which devotes to reducing the trigger delay.Good symmetry of the MDC reduces the hardware storage required for the pattern matching logic.Aiming at the low accuracy of the existing pattern matching algorithm in reconstructing transverse momentum,this paper proposes a two-level pattern matching track reconstruction scheme.The first-level pattern matching uses a pattern library with larger granularity for tracking,and the second-level pattern matching uses a smaller-grained pattern library for transverse momentum reconstruction.While meeting the standard of the traverse reconstruction,the scheme also retains low complexity of the pattern matching algorithm.(2)Reconstruction algorithm of particle hit time in main drift chamber:Referring to the off-line reconstruction algorithm of event start time of similar experimental cases,this paper proposes a scheme to calculate particle hit time based on the track parameters obtained from the reconstruction.Utilizing the track parameters of the charged particles on the r-φ plane,a small section of the track is approximated as a straight line,and the drift distance of the partial hit of the MDC can be calculated.The relationship between the drift time and the drift distance is fitted through a quadratic function.And the drift time of the drift cell hits is calculated to obtain the particle hit time.To achieve the goal of low latency in the trigger system,FPGA acceleration logic employs a variety of methods to reduce circuit latency.In the logic of calculating the azimuth angle and drift distance,the work in this paper uses the quadratic polynomial piecewise interpolation approximation to reduce the delay required by trigonometric functions and division operations on the premise of ensuring accuracy.The median of the sequence needs to be calculated in the reconstruction of the particle hit time,and the bitonic sorting network is used in the logic to accelerate the sorting algorithm.After completing the Python program and FPGA logic design of the above algorithms,this paper examines them using physical event generated by Monte Carlo simulations.The results show that the reconstructed azimuth accuracy satisfies the matching of the track and the calorimeter cluster.For the particles with transverse momentum greater than 180 MeV,the reconstructed particle hit time accuracy is better than 7 ns.The processing results of the FPGA logic are consistent with the results of the Python program,meeting the performance requirements of the MDC sub-trigger.Through static timing analysis and actual measurement on the development board,the trigger logic can run under the system clock with a period of 3 ns,the track reconstruction logic delay is 339 ns,and the time reconstruction logic delay is 207 ns,achieving the goal that the trigger delay is less than 1 μs.In order to reduce the false trigger rate and compress the event data in the high luminosity environment,this work designs and implements the key MDC sub-detector trigger track reconstruction and particle time reconstruction algorithms,and completes the FPGA acceleration logic.The study provides a technical basis for the subsequent engineering design of STCF MDC sub-trigger.