Research Of Effective Fault-tolerant Circuits Based On Quantum Logic Synthesis

In recent years,the extremely large amounts of data generated by human society has enabled artificial intelligence technology to offer strong support for the upgrading of manufacturing industries.However,the performance of computing and storage have turned into a bottleneck for classical computer.The level of integration for a core processor has been increasingly high such that uncontrollable quantum effects make the calculation become invalid.Because of these defects of classical computer,exploring revolutionary technologies for storage and computing has become a hot topic in the field of computer research.In recent years,by using the laws of quantum mechanics,a quantum computer has proven to be stronger for storing and processing information compared with the classical computer.In additional,this kind of computing device has unparalleled advantages in some high-speed mathematics and logic computation tasks.This dissertation focuses on the key technologies for realizing a fault-tolerant quantum computer.By introducing quantum logic synthesis algorithms and the neural network method,we focus on the problems come from fault-tolerant quantum code conversion,universal fault-tolerant quantum computing and quantum error correction process.The main contents of this dissertation are shown as follows:1.For a given quantum code,this dissertation follows the pieceable fault-tolerant protocol to design a heuristic search algorithm for searching its round-robin logical controlledZ gate.Next,this dissertation designs two pieceable fault-tolerant logical controlled-NOT gates between 5-qubit code and Steane-7 qubit code by this algorithm.Besides,this dissertation improve the constant stabilizer error correction processes of these controlled-NOT circuits to ensure that they will not be disturbed by idle qubit errors.Therefore,these controlled-NOT circuits can be modeled as basic fault-tolerant components and used to construct a large-scale logical quantum circuit.Finally,this dissertation designs an efficient fault-tolerant conversion circuit between these two codes with these controlled-NOT circuits.2.This dissertation adopts non-uniform concatenation scheme to design a 2-level concatenated 25-qubit code.Then it realize a pieceable fault-tolerant logical T gate on this code,and propose a fault-tolerant universal computing scheme with lower qubit overhead.Specially,our logical T circuit includes the code conversion sub-circuits acting on the inner logical qubit.In order to overcome the low fault-tolerance of the conversion circuit,this dissertation designs a neural-network-based decoder for such circuit that with a pieceable fault-tolerant structure.The numerical simulation results of the logical T gate further verify the effectiveness of our decoder.3.This dissertation designs a decoder for a syndrome extraction circuit that consumes less resources by using a neural network method.From the numerical simulation results of the basic encoded state preparation circuits,we verify that our decoder can effectively improve the stability of this syndrome extraction circuit.4.This dissertation explores the decoding process of the concatenation code,and analyze the relationship between syndromes that come from different encoding levels and the error propagation event.Then it designs a neural network decoder for a concatenation code.Finally,this dissertation simulates the preparation circuit of 25-qubit basic state and observe that our decoder can effectively improve the error threshold of 25-qubit code.