Optimization And Implementation Of Typical Algorithms For Error Correction Coding And Encryption In Modern Communications

Error-correction coding and encryption are two important parts of modern digi-tal communications.This dissertation focuses on the optimization and implementation of the decoding algorithms of non-binary low-density parity-check(NB-LDPC)codes in modern error-correction codes and the post-quantum encryption algorithms based on supersingular isogeny elliptic curves,to deal with the technical bottlenecks of the corresponding modules for high-speed/low-power implementation in modern commu-nication systems.For the NB-LDPC decoding,we propose two low-complexity high-performance decoding algorithms and devise two high-throughput decoding architec-tures for different applications.In terms of the post-quantum encryption,we propose several ultra-fast low-latency modular multipliers and design the fastest software im-plementation of the supersingular isogeny key encapsulation(SIKE).The main contri-bution and innovation are summarized as follows:1.Two high performance and low complexity decoding algorithms are proposed.We introduce,with theoretical justification,a universal scheme called threshold-based shrinking(TS)scheme,which facilitates a significant reduction of computa-tional complexity for decoding of NB-LDPC codes.Besides,we present a modified two-extra-column(TEC)scheme,which helps achieve better decoding performance for higher-order codes.Appling the two schemes to the trellis-based extended min-sum algorithm(T-EMSA),two high-performance low-complexity decoding algo-rithms are obtained,named TEC-TEMSA and TS-TEC-TEMSA.Simulation results and complexity analyses show that the former has superior error floor and the latter shares lower decoding complexity.For a 256-ary(256,203)example code,com-pared to the T-EMSA,the computational complexities of the TEC-TEMSA and TS-TEC-TEMSA are reduced by about 50%and 90%,respectively.Moreover,both of them outperform the T-EMSA by about 0.3d B when the frame error rate(FER)is around 10^-5.2.An efficient check node unit(CNU)architecture is proposed for high-performance high-speed applications.Based on the L-truncation trellis-based min-max decod-ing algorithm(L-TMMA),we propose a new CNU architecture by incorporating al-gorithmic transformation and architectural optimization to further reduce the hard-ware complexity and thereby the critical path without any performance degradation.Synthesis results show that the proposed design achieves less hardware consump-tion and higher clock frequency with a small latency compared to the state-of-the-art.Specifically,it saves more than 1/3 hardware resources compared with its orig-inal one.3.An ultra-high-throughput high-parallel decoder is devised for low-complexity high-speed applications.An improved layered multiple-symbol-reliability weight-ed bit-reliability based(IL-Mw BRB)algorithm is proposed,which results in a faster convergence rate than the Mw BRB algorithm.Based on it,an ultra-high-throughput low-complexity decoder architecture with an efficient partially parallel process-ing schedule is also presented.The synthesis results demonstrate that the pro-posed decoder for an(837,726)quasi-cyclic NB-LDPC code over GF(2⁵)achieves a throughput of 21.66 Gbps and an area efficiency of 4.77 Gbps/M-gates under the TSMC 90 nm CMOS technology.The proposed decoder reaches a throughput of more than 20 Gbps for the first time among the prior NB-LDPC decoders,and the area efficiency is far beyond the state-of-the-art design.4.Ultra-high speed modular multipliers are proposed for supersingular isoge-ny cryptography.For different forms of such prime,we propose three improved modular multiplication algorithms based on an unconventional radix,all of which cost about 20%fewer computations than the prior art.To improve the scalability in hardware implementation,a multi-precision scheme is introduced for the pro-posed algorithms,resulting in three new algorithms.We then present very efficient high-speed modular multiplier architectures for the six algorithms.The FPGA im-plementation results show the proposed multipliers all achieve more than an order of magnitude higher than the state-of-the-art design(the FFM2 modular multiplier).Especially,each of the multi-precision based designs has almost the same resource consumption as the FFM2 does.5.The fastest software implementation is achieved for the SIKE protocol.We pro-pose a new data representation for the supersingular isogeny-based elliptic-curve cryptography(ECC),which can facilitate obtaining faster finite field arithmetic computing.We have implemented all the proposed arithmetic algorithms in C lan-guage and integrated them into the newest SIKE software library.Targeting at the SIKEp751,the experiment results show that on a 2.6GHz Intel Xeon E5-2690 pro-cessor,the software implementation achieves about 1.65x speedup compared to the state-of-the-art implementation.