Study On Structure Design,process And Performance Of Wafer Level Copper Pillar Bump Packaging

Due to the excellent performance,copper pillar bump technology has become a hotspot in the international advanced packaging research with the potential of replacing solder bump and wire bonding interconnection.The development and application of this technology are mainly in Unite States of America,Japan,Korea and China Taiwan.In China mainland there are few studies and applications in this field.Currently,there are key challenges for application of the copper pillar bump packaging,including the stress induced damage of low dielectric(low-k)layer of the chip,excess wafer warpage and high interface contact resistance of sputtered Ti/Al pad.In this study,the three problems were investigated.An innovative structure,copper pillar bump with a pad at the chip side,was proposed to relieve the stress in low-k layer.In order to lower the warpage,the design rule was defined to minimize the polyimide(PI)film coverage rate,meanwhile copper film plating current density and copper film annealing were also optimized.The contact resistance at the sputtered Ti/Al pad interface was decreased by reducing the residual H₂O vapor concentration in the chamber.These results are validated in the commercial products.The details were shown in the following:In the flip chip reflow process,the Finite Element Analysis(FEA)method was used to simulate the influence of the copper pillar bump geometry on the chip low-k layer stress,combined with experiment.The simulation results show that,increasing the copper pillar bump size at the chip side,or decreasing the size of copper pillar bump at the substrate side,decrease stress in the low-k layer.For example,by changing the geometry of the copper pillar bump,tensile stress in plane and out of plane are decreased by 35%and 57%respectively.With 5?m depth undercut the stress is increased by 89%.In the experiment,a novel copper pad structure was proposed and introduced at the chip side of the copper pillar bump to decrease the stress in the low-k layer.The structure of copper pillar bump with copper pad was demonstrated in commercial products successfully.The impact of PI thin film on copper pillar bump wafer warpage was studied.The warpage was measured with defferent PI film geometry,pattern,coverage rate on the wafer and exposure energy.Results show that the coverage rate and the thickness of the PI film are the critical factors for the warpage.For example,the warpage is decreased from 0.013 m^-1 to 0.006 m^-1,when reducing coverage of PI film from 100%to 20.66%.A novel design rule to reduce the warpage was then proposed.Each copper pillar bump stands on a separated PI film.By designing these PI film“Islands”,a low PI film coverage is acquired.In addition,optimizing the PI film pattern contributes to minimizing the leakage current among bumps and avoiding the excess undercut of the sputtered layer.The copper pillar bump wafer warpage and stress were studied with different plating and annealing condition.Copper film was plated with different current density and then stored at room temperature or baked in the oven for annealing.During this period,the warpage was measured.The plated copper was characterized with the Focus Ion Beam(FIB)and Scanning Electron Microscope(SEM).Results show that the copper film plated with high current density has high recrystallization rate,leading to a dramatic tensile stress increase during the initial stage after plating.And the stress is released slowly,stored at room temperature.Plated with low current density,the compressive stress in the copper film is decreased slowly after plating.Baking can speed up the rate of recrystallization of plated copper film,while it will increase the wafer warpage,because of the mismatch of coefficient of thermal expansion between the copper and Si wafer.Therefore,optimizing the current density and annealing conditions at room temperature can decrease the stress of copper film and lower the wafer warpage.These results were also demonstrated in products,solving the passivation layer crack problem caused by high stress during the plated copper annealing.The contact resistance at interface of Ti barrier layer and Al pad was studied.The gas concentration in the sputter equipment chamber was monitored by Residual Gas Analyzer(RGA),the process parameters of the sputter equipment were recorded by Real Time Monitor(RTM)system,and the electrical resistance of copper pillar bump was measured by Kelvin four-probe method.The Multivariate Analysis(MVA)method was used,to analyze the influence of the gas condition and process parameter on the interface contact resistance.The results show high H₂O concentration in wafer prior to sputtering process,is prone to cause the formation of excess oxides on Al pad,which induces unwanted contact resistance.Given this condition,the extra low-temperature sputter equipment is not requisite for lowering the CO concentration to minimize the contact resistance.Lowering the H₂O concentration in wafer can decrease 45%of total resistance of copper pillar bump.It can eliminate the reliance on low-temperature sputtering equipment.