Design Of Laser Driver And Transimpedance Amplifier For Optical Communications

Among the various modulation schemes utilized in optical communication links,on-off keying(OOK)is widely deployed in access and metropolitan networks due to its simplicity and cost-effectiveness.However,the rapid growth of data traffic has motivated the utilization of other modulation schemes with better spectral efficiency.Among them,4-level pulse amplitude modulation(PAM4)has been adopted for high data rate standards because it doubles the transmission bit rate at the same bandwidth,compared to OOK binary modulation.The most common data formats that can be used in OOK and PAM4 modulation schemes are non-return-to-zero(NRZ)and return-to-zero(RZ).The NRZ formats require half the bandwidth compared to 50%RZ formats to transmit the same bit rate.However,they are not recommended in long-haul transmission due to the effect of optical fiber dispersion that broadens the transmitted pulses and causes inter-symbol interference(ISI).Contrarily,RZ formats have a better performance in long-haul applications as they provide shorter pulses,and thereby can mitigate the dispersion effect.This dissertation mainly focuses on the design and implementation of laser diode driver(LDD)circuits and a transimpedance amplifier(TIA)that supports both OOK and PAM4 modulation schemes with either NRZ or RZ data formats.The OOK/PAM4 dual-mode operation makes the designed blocks suitable for optical communication systems with different standards.In this dissertation,four different LDD integrated circuits(ICs)have been designed;three of them were fabricated and tested using chip-on-board assemblies with Rogers RO4350B printed circuit boards(PCBs),whereas the fourth circuit was evaluated using post-layout simulations.The first LDD IC supports both NRZ-OOK and NRZ-PAM4 modes at data rates up to 15 Gbps and 30 Gbps,respectively,and it is implemented in 0.15—?m E-mode pHEMT process.The proposed 30 Gbps NRZ-PAM4 LDD is implemented by combining two 15 Gbps NRZ-OOK LDDs,as the high and low amplification paths,to generate PAM4 output current signal with levels of 0,40,80,and 120 mA when driving 25-? lasers.The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD.The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage.The output transmission-line back-termination,which absorbs signal reflections from the imperfectly matched load,is performed passively with on-chip 50-? resistors.The measurement results show clear output eye diagrams at speeds up to 15 Gbps and 30 Gbps for the NRZ-OOK and NRZ-PAM4 drivers,respectively.At a maximum output current of 120 mA,the driver consumes 1.228 W from a single supply voltage of-5.2 V.The proposed driver shows a high current driving capability with a better output power to power dissipation ratio,which makes it suitable for driving high current distributed feedback(DFB)lasers.The chip occupies a total area of 0.7×1.3mm2.The second LDD IC is also fabricated using 0.15-?m E-mode pHEMT process,and it supports RZ-OOK and RZ-PAM4 modes at data rates of 2.5 Gbps and 5 Gbps,respectively.The reported RZ LDD increases the integration level by providing a single-chip solution in which an NRZ-to-RZ converter and a high current LDD are combined.The output RZ signals have a duty cycle of 33%(132 ps),which makes the proposed RZ driver suitable for long-haul optical communication systems.The maximum output current is as high as 120 mA,making the driver a good candidate for driving high current DFB lasers that could be biased to operate in gain switching mode for further improvement in the transmission distance.Measurement results show clear electrical output eye diagrams with rise/fall times below 38 ps.The total power consumption is 1.3 W from a supply voltage of-1.9 V for the NRZ-to-RZ converter and-5 V for the LDD.The chip occupies a total area of 1.2×2.7 mm2.The third LDD IC is designed and tested using 0.13-?m SOI CMOS process.Similar to the second LDD,this driver also supports 2.5 Gbps RZ-OOK and 5 Gbps RZ-PAM4 operation.However,the output current here is boosted to 135 mA,and the duty cycle of the output RZ signal can be adjusted within 25-50%range using a voltage-controlled delay line.Moreover,the driver utilizes an active back termination(ABT)circuit to absorb loading reflection due to the imperfect match at the laser side.Clear output electrical eye diagrams are measured with rise/fall times below 50 ps.At a maximum output current of 135 mA,the RZ-LDD consumes 1.455 W.The total chip area is 1.8×2.6 mm2.The fourth LDD circuit operates at 10 Gbps NRZ-OOK,and it is designed in 0.13-?m SOI CMOS technology.The driver utilizes cross-coupled neutralization capacitors and integrates a tunable negative capacitance circuit to extend the bandwidth.The LDD can deliver a modulation current ranges from 10 to 150 mA to 25-? lasers with a preserved dynamic performance due to the usage of a segmented output driver scheme.The driver supports DC and AC coupling to 25-? lasers with a total power dissipation of 1.06 and 0.72 W,respectively at maximum output current.The physical layout occupies an area of 0.84×0.9 mm2.Finally,the dissertation discusses the design of high sensitivity and dynamic range 25 Gbps NRZ-OOK,50 Gbps NRZ-PAM4 TIA in 40-nm CMOS process.The noise and bandwidth are both optimized by adopting a high gain low bandwidth transimpedance stage followed by three continuous-time linear equalizer(CTLE)stages to restore the bandwidth.The proposed TIA employs two separate automatic gain control(AGC)loops,which control the inverter-based transimpedance stage and four subsequent variable gain amplifiers(VGA)stages,to achieve low noise and high linearity operation.The proposed TIA also employs an automatic offset cancellation(AOC)loop.Post-layout simulation results show that the TIA achieves a maximum transimpedance gain of 78 dB?,a 3-dB bandwidth of 19.8 GHz,an average input-referred noise current density of 16 pA/? Hz with a photodiode and bonding pad capacitances of 120 fF and 40 fF,respectively.The total harmonic distortion is less than 5%for 250 mVpp differential output swing and 1.12 mApp input current.The output buffer provides a fully differential voltage swing of 600 mVpp and the total power consumption of the circuit equals 65 mW.