Hardware/Software Co-design Of System-on-Chip Based On Graph Convolutional Network

With the increasing scale of embedded system,the design complexity of System on Chip(SoC)also become sophisticated.Since the 1980s,Hardware/Software(HW/SW)Co-design has become a new methodology to design complex embedded systems.After several generations,the HW/SW co-design gradually develops towards the direction of full automation process.One of the key topics to be investigated in HW/SW co-design is HW/SW partitioning,which can significantly reduce the time of SoC design and improves the performance of an embedded system.However,the majority of partitioning schemes have large exploration time and generate often low-quality solutions for large-scale systems.Besides,the security of embedded systems is also facing huge challenges.In terms of identity authentication,digital signature algorithms have been widely used in a variety of systems to protect the security of data.In the field of the information security field,the digital signature SoC system plays an important role in ensuring the security of data.Most previous works of HW/SW partitioning still rely on the experience of engineers,and software design is often carried out after hardware design,which prolongs the development period and reduces the efficiency of system design.The existing technology of SoC HW/SW co-design does not form a complete and unified verification process,which makes the verification process tedious and inefficient.Focus on the above problems,we firstly study the task classification based on transfer learning and dictionary learning.From the perspective of graph classification,we extend it to node classification,and then to the study of HW/SW partitioning.Two different classification models are designed.Secondly,we construct an SoC system architecture according to the design requirements.And we propose a fast HW/SW partitioning approach-GCPS,based on graph convolution network(GCN)to address these problems.To this end,we generate a partitioning model by using constructed GCN.The purpose is to maximize the usage of hardware area and rapidly finding the optimal partitioning scheme.Based on static priority and the LSSP algorithm,we integrate the scheduling into the partitioning process,which is used to quantify the quality of solutions and also improve the task execution efficiency.The result of scheduling is also feed back to partitioning model.The GCPS model is applied to the digital signature system.Finally,we realize the SoC HW/SW co-design and verification.The innovations and main contribution of this paper are as follows:(1)In view of the low-efficiency of traditional machine learning methods in large-scale systems,this paper first studies the task classification problem based on transfer learning,and designs a DMTTL model based on transfer learning and dictionary learning.Through the characteristics of transfer learning and parallel execution,the classification performance and running efficiency of the system are improved.On the other hand,the tasks with graph structure are further considered,and a model——GMADL based on multi-view dictionary learning is designed,and its classification effect is better than most of the latest graph classification models.Through the introduction of multi-view,the GMADL model has strong expansibility,and the GMADL model can also be applied to the node classification problem.Therefore,this paper also improves the GMADL model,puts forward the NMADL node classification model,verifies and analyzes it,studies the feasibility of the model in the HW/SW partitioning problem,and provides necessary theoretical and experimental support for the follow-up work.(2)To solve the problems of high complexity of large-scale system design and low efficiency of HW/SW partitioning,we propose a fast HW/SW partitioning approach based on GCN——GCPS,which is suitable for large-scale systems.Since GCN can effectively process the graph data,and aggregate the characteristics of neighbor nodes to generate a new node representation.GCN works well for node classification and is available to make the model converges rapidly.Firstly,we formulate the partitioning problem as an optimization problem to minimize the execution time of all tasks under a hardware area constraint.Secondly,a gradient-based approach is utilized to deal with this optimization problem.Especially for large-scale systems,this method is more efficient than the traditional heuristic algorithms.(3)In order to further improve the performance of HW/SW partitioning and reduce the execution time of the system through parallelization,the scheduling is designed and carried out after the HW/SW partitioning.The static priority of each node is calculated,and the scheduling algorithm based on static priority is designed to quantify the quality of solutions and further shortens the execution time.The optimal scheduling of the system task graph is achieved by minimizing task execution time and maximizing utilization of hardware resources under the hardware area constraints.(4)To further enhance the security of the digital signature system,this paper improves the ECDSA algorithm,designs the protection tricks in the preprocessing stage of plaintext,and realizes the HW/SW co-design of the digital signature system.After constructing task graph,partitioning and scheduling,for digital signature system applications,we use the co-design technology to apply the GCPS model to the partitioning process.Then,we implement the software design,hardware design,interface design,and HW/SW synthesis.We use C/C++and Verilog programming languages to implement ECDSA digital signature algorithm.(5)Aiming at the problems of low efficiency and non-uniform flow of SoC HW/SW co-verification,a collaborative simulation verification platform is constructed,the sharing of test vectors and input data is realized by designing PLI/VPI interface,and test vectors are randomly generated by high-level language model to improve the efficiency of system verification.A complete and unified SoC HW/SW co-verification process is studied.The verification of the system design can achieve real-time bit-level verification,and the problems existing in the HW/SW co-design process can be fed back in time.The integrated verification platform improves the verification efficiency of the system.