Design Of Self-Aligned Programmable Delay Chip For Quantum Key Distribution System

The gated single-photon detector is commonly used in current quantum key distribution,the detector can respond only when the quantum light pulse reaches a small time window(gating window)of the detector.The difference path between the signal light and the synchronization light or others leads to the gate signal often not being accurately aligned with the quantum light pulse.Therefore,the programmable delay circuit is needed to achieve precise al ignment of the gating control signal and the quan-tum light pulse in detector.It is also used in circuits such as forming narrow pulses driven by light sources.As the repetition frequency of the quantum light pulse becomes higher and higher,the programmable delay circuit with high linearity and higher operating frequency can effectively improve the performance and stability of the quantum key distribution.The programmable delay chip and its key modules based on a delay locked loop without off-chip calibration are focused on in this dissertation.Based on the SMIC 55nm 1P7M CMOS process,dual channel programmable clock delay chip is proposed,which can be configured in one of two operating mode.In the dual delay mode,the dynamic delay range is 0ns?5ns,the dynamic delay range is 0ns?10ns in the extended delay mode.Delay chain structure is used to achieve a large dynamic range in the coarse stage,and an adjustable load capacitance mechanism is applied to improve the delay resolution in the fine stage.In view of larger operating temperature range and the larger process deviation,the coarse delay locked loop and fine delay locked loop are respectively proposed to control the delay of the coarse delay stage and fine delay stage to adapt to operating temperature range and process deviations.At the same time,a voltage-controlled coarse delay unit and a voltage-controlled fine delay unit suitable for high-frequency operation are proposed.The charge pump-based phase-locked loop is adopted for the low jitter clock module.In the ring oscillator,an error amplifier is applied to improve the linearity of the KVCO curve,the enable signal is added to meet the oscillation conditions,based on the combination of capacitor array and tail current for frequency tuning,a dual-switch digital capacitor array tuning method is proposed,which can increase the frequency tuning range while the center frequency and the gain of tuning curve remain,unchanged.Based on the power requirements of the system,a power supply network including a power detection,a bandgap reference,and a low-dropout linear regulator is proposed.A LDO structure with adaptive bias buffer stage structure is improved to ensure the stability of the loop to solve the mismatch between current load capacity and current efficiency.The power PMOST is divided into two parts to avoid a large current during the power-on process.During the power-on period,only the small-size power PMOST is turned on,and then the large-size power PMOST is turned on after the power is com-pleted.The load regulation rate can reach-0.03mV/mA@0?20mA.The worst power supply rejection ratio can reach 66dB at low frequency.After theoretical analysis,simulation verification,chip design verification and detailed testing,the proposed programmable delay chip in this dissertation achieves a resolution of 9.77ps(step),which can be adapted to-40?85? temperature range and 3.3±0.3V power supply voltage range,its operating frequency range is 50MHz?1.5GHz.The chip area is 2.0475mm2(including 10 PAD),core area is 0.76mm2.At 1.5GHz operating frequency,the INL of channel 0 is 1.60LSB and the INL of channel 1 is-1.08LSB.In extended delay mode,INL is 2.20LSB@1.5G.The RMS jitter of channel 0 is 8.68ps@100MHz and 7.23ps@1.5G.The RMS jitter of channel 1 is 6.18ps@625MHz,7.09ps@1.25GHz.