| This work explores new RET devices and circuit design strategies that address the above limitations. The primary contributions of this dissertation are threefold. First, a RET device capable of restoring energy in these systems is designed and experimentally demonstrated. This device enables cascading and feedback in RET logic, two circuit design concepts commonly used in large-scale digital systems. Second, a new style of RET logic design, called Pre-Charge Logic (PCL), is introduced. PCL addresses both forms of signal loss while simultaneously providing a library of cascadable RET logic gates, many of which cannot be implemented using previous methods of RET logic design. Third, the design methods of PCL are explored and validated by simulation and experimental demonstration. Continuous-time Markov chain modeling confirms that the proposed PCL devices perform their intended Boolean operations, while an experimental demonstration of a PCL PASS gate substantiates the underlying operating principles of these devices. Collectively, these contributions pave the way for developing larger, more complex RET systems in the future. |
