Fault Diagnosis in Digital Circuit

The goals of fault diagnosis are to ascertain whether faults are present in (fault detection) and to identify them (fault location). Fault location is commonly performed with the aid of a fault dictionary. Fault dictionaries are constructed via fault simulation under the single fault assumption. The single fault-model often assumes a circuit is tested often enough such that no more than one physical defect is likely to occur between two consecutive test applications. This strategy is not valid when one physical defect manifests itself as multiple faults. It is observed that the presence of redundant faults also invalidates the frequent testing strategy, since a redundant fault may mask the existence of a detectable fault. In all these situations, a multiple fault model is required. However, in almost all practical cases a fault dictionary for multiple faults is infeasible to generate due to an exponential number of equivalence classes.;In this dissertation, we first present a VHDL-based CAD tool that integrates design error injection, simulation, and diagnosis for digital circuits. The tool uses an FPGA-based board to inject error models in the design and compute the error free and erroneous signatures of internal lines. The signatures are later used for detection and diagnosis of errors for the circuit under test (CUT). Several experiments were conducted to demonstrate the capabilities of the tool. The obtained results demonstrate that the tool could detect and locate the source faulty node(s) within the CUT.;Then, a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm, which processes the actual response (effect) of CUT, to determine fault situations (causes). The main tool of our approach processes the response to deduce the internal signal values.;A multiple stuck at fault model is implicitly employed and no-fault enumeration is required. The enhanced deduction algorithm is applicable to complicated combinational circuits. The internal values obtained are used to determine fault situations in CUT compatible with the applied test T and the response. Our analysis can identify fault locations and values (s-a-0 or s-a-1). Our main result is that any stuck fault can be diagnosed. Preliminary results demonstrate that our technique always achieves great accuracy for detecting and locating the faults, saving a large amount of time, especially for more complicated combinational circuits. The problems solved by our procedure are using deterministic test vectors.;We next present a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm and a backtracking strategy which can be regarded as a recursive process of value justification in which we first justify (explain) the values obtained at the primary outputs (POs). To justify a (0) value on the output of a- NAND gate (assuming it is normal), we need all the gate inputs to be (1). To justify a (1) value we need at least one input to have value (0). All the known values of internal normal lines must be justified by values of their predecessors. When both 0 and 1 values have been deduced for a gate output and it is critical, it is identified as normal and all its currently known values are analyzed.;In some cases, we need to decide to select one of the possible ways to justify a (1) value on the output of a- NAND gate. if a decision leads to an inconsistency (self-contradictory state) with the forward propagated value, the algorithm will backtrack to the last decision point and try an alternative decision. After a decision is made, all the implications resulting from that decision are performed. If no inconsistency is detected, a new decision point is necessary. Otherwise, a solution has been obtained. A solution is a set of values which could have occurred in the CUT, that is, a possible set of actual values. The main tool of our approach processes the response to deduce the internal signal values in all possible solutions.