| This work establishes improved techniques for designing concurrent testing and checking in computer systems. At the logic circuit level, this study advances the design of self-checking circuits by introducing quantitative measures and figures of merit for self-checking power. At the computer system level, this study addresses the use of watchdog processors for error-detection performed during the execution of computer programs.;Above the circuit level, concurrent testing is needed to detect errors in function resulting from faults that are not included in the fault sets assumed in circuit design. This study examines the application of watchdog processors in concurrent testing at the system level. Watchdog processors, an extension of the concept of watchdog timers, are auxiliary processors that perform detection of errors in high level behavior during the execution of computer programs. This study introduces structural integrity checking, SIC, an error-detection technique that recognizes high level control flow structures in programs written under the software design discipline known as structured programming. SIC labels these structures to facilitate detection of structural errors, and checks the labels during execution by using a watchdog processor. This study establishes a formal description of SIC, explores implementation issues, and presents the results from an experimental implementation of SIC.;The use of self-checking circuits in computer systems requires quantitative measurement of the self-testing and fault-secure properties of the self-checking circuits. In this study, the quantitative measures TIF, testing input fraction, and SIF, secure input fraction, are defined to provide comparison of self-checking circuit designs. Figures of self-checking merit are defined to summarize data from evaluation of these measures. Figures of merit based on simple averages of the measures can conceal important differences between designs. This problem is solved by defining figures of merit that emphasize low values of the measures. This study evaluates three designs for self-checking implementations of linear feedback shift registers, LFSRs, used as cyclic redundancy code encoders. The number of distinct input patterns for an LFSR can be very large. In this study, theoretical analysis reduces the task of evaluation to operations small enough to be executed by a computer. |
