| A computer hardware description language (CHDL) and its compiler/simulator system, designed for student use at graduate and undergraduate levels are described. The system is usable above the switching circuit level and incorporates features to investigate designs using microprogrammable components including bit-sliced chips such as the AMD-2900.; The order of execution in the simulator is controlled by an event table using each time/component as a separate event. The handling of event timing for items copied from the library of components is unique in that the individual times may be changed as they are copied into the active file. The system also allows the user to make several copies with a single statement and adjust the timing of each copied item separately.; The LALR formal grammar, presented in the Appendix, was developed to make the English-like language follow as closely as possible the hierarchic structure of the system being described. This supports a hierarchic design process through the system, programming and register transfer levels. Use of the language below the bit level has not been investigated.; The contents of the main memory, micromemory and up to three (3) auxiliary memories are developed separately and read from files into the program memory prior to simulation. The simulation driver incorporates breakpoints, trace, display and other tools needed to follow the simulation which may be carried out in either step-wise or run-to-break fashion. The interactive system is written in Cobol and resides on the DEC-20.; The system has been used one semester for a graduate course in computer organization. The User's Manual (Appendix 6) contains examples from flip-flops to microprogramming and show examples, diagrams, explanations, and coded descriptions of the logical device. |
