Spatial light modulator with silicon integrated on electro-optic lead-lanthanum zicronate-titanate

The integration of silicon and electro-optic lead-lanthanum zicronate titanate (PLZT) is studied in order to fabricate a spatial light modulator (SLM). On the silicon, optical detectors and drivers will be fabricated. On the PLZT, optical modulators will be fabricated. The thermal properties of PLZT were measured in order to evaluate the temperature this material experiences during the laser crystallization process of silicon. Chemical vapor deposition (CVD) was used to deposit {dollar}SiOsb2{dollar} and polysilicon on PLZT. However, better quality Si is required for the SLM we proposed. Laser crystallization is applied to improve the quality. The critical issue in this process is to crystallize Si at 1420{dollar}spcirc{dollar}C without raising the temperature of PLZT above 900{dollar}spcirc{dollar}C in order to avoid damaging the PLZT. These issues were addressed through different techniques.; Damage free PLZT in the crystallization process was obtained by applying a 3.5 {dollar}mu{dollar}m thick SiO{dollar}sb2{dollar} layer as a thermal buffer layer. A theoretical approximation is used to estimate 0.1 ms beam dwell time to prevent {dollar}SiOsb2{dollar}/PLZT interface reaching 900{dollar}spcirc{dollar}C. A beam shaping mask is used to confine the laser beam to satisfy 0.1 ms beam dwell time requirement. The beam shaping technique is also used to improve the surface smoothness in laser crystallization. Antireflection stripe is used to define the grain growth and enlarge the grain size. Second beam assisted laser crystallization is used to reduce the film stress and enlarge the grain size up to 25{dollar}mu{dollar}m by 125 {dollar}mu{dollar}m. Raman spectroscopy was used to measure the stress of the films by different crystallization techniques.; NMOS transistor is fabricated by laser assisted diffusion for electrically addressed spatial light modulator, and have a breakdown voltage up to 50 V and a transconductance up to 200 at gate voltage of 9 V. The electrically addressed spatial light modulator possesses a contrast ratio up to 35:1. NMOS, PMOS and detector were fabricated by ion implantation for optically addressed spatial light modulator. The NMOS by ion implantation has a breakdown voltage of up to 42 volts and a transconductance up to 220 {dollar}mu{dollar}S at gate voltage of 9 V. The PMOS has a breakdown voltage of 23 V and transconductance up to 7.5 {dollar}mu{dollar}S at gate voltage of 9 V. The responsivity of the detector is 5.6 A/W. An optically addressed spatial light modulator of a 16 x 16 array with a detector and a transistor per cell performs modulation with a contrast ratio up to 26:1. A sensitivity enhanced optically addressed spatial light modulator of a 6 x 8 array with positive feedback circuitry in each cell modulates with a contrast ratio up to 50:1.