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Fault location and parameter identification in analog circuits

Posted on:1991-12-29Degree:Ph.DType:Dissertation
University:Ohio UniversityCandidate:El-Gamal, Mohamed Abd El-AzizFull Text:PDF
GTID:1478390017450724Subject:Engineering
Abstract/Summary:
The objective of this dissertation is to develop new simulation--before--test (SBT) as well as simulation--after--test (SAT) methods for fault diagnosis of analog circuits. The emphasis in all the developed methods is on overcoming the following three major problems in analog fault diagnosis: (1) The nonlinearity of the diagnosis equations; (2) The limited number of nodes accessible for measurements and excitations; (3) The large number of fault simulations that has to be performed in the simulation--before--test methods.; The developed methods should, therefore, diagnose the faults using only linear equations even for nonlinear circuits. This can dramatically decrease the computational effort involved in the solution process. At the same time, the ability to locate the faults solving only a linear system of equations should not be achieved at the expense of increasing the number of measurement nodes. Accordingly, the developed methods must fully exploit the available measurement nodes to generate the necessary independent information needed for fault diagnosis. Moreover, a moderate number of fault simulations should be used in the developed SBT methods without affecting the degree of fault isolation.; In order to realize the dissertation's objective, fault verification and element identification methods are developed. A neural network approach for analog testing is also proposed.; In fault verification, topological conditions for circuit diagnosability are derived. These conditions depend only on the graph of the circuit and not on element values. The derived conditions are applicable for passive and active circuits. Therefore, they provide a unified graph theoretical approach for the diagnosability of analog circuits.; Fault diagnosis in nonlinear resistive circuits is the second SAT approach presented in this dissertation. A fault verification method and a parameter identification method are developed for this type of circuits. Faults are diagnosed in both methods by solving a linear system of equations. The nonlinearity of the circuit elements is also exploited to produce a large number of independent measurements.; Two new SBT approaches which utilize the parallel information processing capabilities of artificial neural networks are developed. The diagnosis problem is formulated and efficiently solved in a neural network context. The nonlinear mapping between the measurement space and the element space is realized through training examples. This mapping can then be used to diagnose a larger number of fault cases than those presented in the training of a neural network.; A neural network model is also presented and its potential in solving the circuit diagnosis problem is demonstrated, providing accurate fault identification with exceptional learning and testing speed.
Keywords/Search Tags:Fault, Diagnosis, Circuit, Identification, Methods, Analog, SBT, Neural network
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