PMSCA: A content addressable memory-based high-performance Prolog machine

A content addressable memory (CAM)-based architecture for Prolog is presented. The architecture employs OR-parallelism inherent in Prolog. Some Prolog architectures and models which are used as the basis of the design of the PMSCA (Prolog Machine based on a Semi-systolic array and a CAM Architecture) are described. Other well-known Prolog machines are briefly introduced and some of them are used later for performance comparisons.;A CAM-based Prolog architecture based on the model is designed. The CAM-based architecture reduces not only the total number of argument accesses, but also the total number of Prolog clause head accesses. Also, the CAM-based architecture supports efficient backtracking and fast garbage-collection. A semi-systolic array architecture is added in order to obtain another performance improvement, and is used to check unification operations. The PMSCA is compared with other Prolog machines for the performance evaluation. The comparison results proves that the PMSCA is a high performance Prolog machine.;A model based on a depth-first searching strategy and an OR-parallelism is developed for the PMSCA. The depth-first searching strategy eliminates overheads due to scheduling. The OR-parallelism contributes to improving performance by executing Prolog programs in a OR-parallel fashion. A case study is represented in order to help readers' understanding.