Dipole heterostructure field effect transistors

We have proposed a new class of devices, the dipole Heterostructure Field Effect Transistors (dipole HFETs), which use both planar doped n- and p-planes in the charge control layer. The devices are intended to reduce the gate leakage current for the enhancement-mode and the real space transfer effect in the depletion-mode devices. Both theoretical and experimental studies of the dipole HFETs have been carried out primarily in n-channel AlGaAs/GaAs HFETs.;A computer program for solving the one-dimensional Schrodinger and Poisson equations of the heterostructure systems has been developed for studying the theoretical aspects of the HFETs. The results show that the presence of p-plane enhances the effective Schottky barrier height in the enhancement-mode HFET, and provides better carrier confinement to the GaAs interface well in the depletion-mode dipole HFET. This in turn leads to reduced forward bias gate current in E-mode devices and reduced parallel conduction and real space transfer in D-mode devices. An analytical model based on the depletion approximation is also provided. Both theoretical models are used to optimize the position of the p-plane in n-channel devices.;The enhancement-mode dipole HFETs fabricated with a self-aligned process show that the gate current is reduced at 1.2 V by an order of magnitude when compared with a conventional enhancement-mode HFET, indicating the enhanced effective Schottky barrier height. The dipole HFET has not only a comparable device transconductance but a much broader transconductance peak. The maximum drain saturation current is substantially higher, and there is no negative transconductance region even at 2.5 V gate voltage.;The depletion-mode dipole HFETs fabricated by the conventional gate recess process have a cut-off frequency of 14GHz and maximum oscillation frequency of 24GHz for the 1...