| Solid state transformer (SST) is considered an emerging and disruptive power electronics technology for medium voltage (MV) (2 kV-35 kV) applications including smart distribution system, traction transformer, ship power and renewable energy. SST concept is proposed that aims to replace conventional line frequency transformer (LFT), providing many advanced features such as VAR compensation, voltage regulation, fault isolation, and DC connectivity. However, many challenges related to high voltage stress, efficiency, reliability, protection and insulation must be addressed before the technology is ready for deployment.;Three-stage SST with ac-dc-dc-ac scheme is the most widely studied and adopted approach since it can achieve most of the smart features and owns best control flexibility. However, the major disadvantage of this scheme is reduced efficiency due to multiple stages of power conversion. In addition, complex circuit and control configurations limit the system power density. Direct AC-AC converter, named as direct AC-AC transformer (DACX), with one stage of power conversion is desirable in MV applications where higher efficiency is preferred and only limited smart features are needed. In general, two major technical challenges in MV direct AC-AC converter needs to be addressed: (1) wide voltage range leads to a much more complex ZVS circumstance, (2) requirement in capacitance reduction to reduce unwanted reactive power and MV capacitor's size/weight.;A novel current fed series resonant converter (CFSRC) is proposed for the first time that can address many technical challenges in DACX applications. (1) It helps MV MOSFETs achieve ZVS operation under wide input voltage and load range. Thus, higher switching frequency can be achieved. (2) This topology helps minimize system total required capacitance, which helps improve system power density and reduce unwanted reactive power. Theoretical time domain analysis and fundamental harmonic approximation (FHA) are conducted, providing design equations for switching frequency selection.;The 15 kV SiC MOSFETs developed by Wolfspeed enable simple and robust two-level DACX where the peak voltage stress is less than 12 kV. Chapter 3 revisited the characterizations of 15 kV SiC MOSFETs including switching loss, Ron, thermal, output charge and package. ZVS design of 15 kV SiC MOSFET is studied and analyzed under wide input voltage condition (0 to 10 kV). Constant deadtime strategy is proposed, with which ZVS can be realized at most of high voltage range. Partial discharge occurs when input voltage is low. However, only neglectable associate switching loss will be generated if deadtime and Lm are properly designed. Detailed analysis of ZVS behavior under wide range of voltage conditions and detailed calculation of associated loss from partial ZVS are presented. System parameters including Lm and tdead are optimized based on tradeoff between turn on loss and conduction loss.;Resonant capacitors are distributed on both sides of the transformer to minimize number of MV MF SiC MOSFETs. Inherent cycle by cycle current-limit capability is achieved by paralleling diodes on low voltage (LV) resonant capacitors. The theoretical analysis and design of DACX under overload and short circuit conditions are conducted. Equation for peak current calculation under short circuit is also provided. The calculation results show that the peak current is a function of the input voltage, resonant inductance and primary resonant capacitance. With proper design of the resonant tank, the expected peak MV MOSFETs current under 7.2 kV short circuit will be less than 40 A. |
