Large area MOS power device technology

Power devices with high current carrying capability are required for applications like motor control, traction, HVDC and electric cars. MOS-gated power devices offer an attractive alternative to gate turn-off thyristors for these applications due to their high input impedance, better safe operating area and ease of paralleling. However, the current handling capability of these devices is limited by their yield. An important reason for yield loss in MOS gated power devices is the presence of gate to source shorts. The traditional approach to increasing the yield uses improved processing technology to reduce the defect density.; In this dissertation, new design techniques for increasing the yield of MOS-gated power devices are discussed. These designs partition the device into small segments and use wafer repair techniques to isolate the defective segments from the rest of the device. The design using low current fusible links also has a self repairing feature, which causes gate to shorts that arise during device operation to be disabled. The isolation of defective segments is carried out using fusible links or built-in circuits. The analysis, design and fabrication of fusible links are discussed. Power MOSFETs and IGBTs have been designed and fabricated using some of the proposed designs. Defective segments have been successfully isolated to produce devices with significantly reduced gate leakage currents. These new designs can be used to fabricate large area power MOSFETs, IGBTs and MOS-gated thyristors.; A test element group for analyzing gate to source shorts in MOS-gated power devices has been designed and fabricated. This test element group allows the separation of yield loss due to defects at the gate periphery from defects in the gate surface area. This test element group is generally useful for monitoring yield loss mechanisms when manufacturing power devices. The results obtained from measurements on 10400 devices indicate that gate to source shorts occur mainly along the edge of the polysilicon gate. No significant difference in defect density was found between devices using different interlevel dielectrics. The contact window opening step has been found to have a strong influence on the density of gate to source shorts. The effect of defects in the edge termination on breakdown voltage was studied. In many cases, defects in edge terminations were found to have no effect on the yield.; A methodology for maximization of the active area in the large area device designs has been developed. This procedure takes into account the area loss due to the partitioning of the device, and the yield of the individual segments, which depends upon the defect density. For small segment sizes, the active area is reduced due to the area consumed by the device partitioning, while for large segment sizes, the active area is reduced due to lower segment yield. Consequently, it has been found that an optimum segment size exists at which the active area is maximized. It has been found that by proper selection of the segment size and layout, the area loss in the large area device designs could be reduced to less than 5%.