| The past four decades have witnessed significant developments in the electronics packaging industry. The need for lower cost and advanced functionality in terms of faster speed, higher density, packed in a smaller form factor have been the key driving factors of this evolution. Even though advances in chip technology are promising, the market demand rate has always been higher. Moreover, achieving required scalability without affecting reliability and cost are some of the major challenges that manufacturers have always faced. While the electronics packaging industry is trying to overcome the reliability and yield related challenges for the transition towards 3D integration, alternative board level stacking techniques are proving useful for satisfying the customer demands of higher density, faster speeds and reduced form factor in the case of memory systems. This has led to significant developments in stacking technologies which are serving as an alternate way to satisfy market demands.;Module level stacking technologies, using flexible as well as rigid substrates, have been proven to be successful for increasing density without significantly increasing the real estate. Similarly, for over a decade, device level stacking approaches, such as Package-on-Package (PoP), have been proven to be useful in a large number of instances. However, both these stacking technologies have concerns related to reliability, yield or manufacturing flexibility at the board level manufacturers end. Therefore, an alternative device stacking methodology, which is completely compatible with the generic SMT process, is proposed in this research.;A new technology, named the High Density STEP module, is being developed to satisfy above mentioned market needs. Since the devices and the interposers are arranged in a STEP formation to increase the module's density, this assembly has been named as the High Density STEP module. The T-shaped PCB interposer and the research associated with the development of the SMT processes in order to create a manufacturable and reliable product are unique factors of this research.;A High Density STEP module increases the memory density compared to a standard module by placing a T-shaped interposer in the available space between adjacent memory devices, without affecting the standard form factor. The complex structure and the assembly process might pose a variety of challenges related to the assembly process, performance and the reliability of the end product. Therefore, the primary objectives of this research focus on developing a defect free assembly process, enhancing the thermal performance by establishing cooling guidelines and evaluation of the solder joint reliability of the STEP module. This type of device stacking approach is relatively new and has not been thoroughly researched. Therefore, there is a need to conduct systematic research that can help to standardize the manufacturing processes with an aim to achieve a reliable product which is the primary goal of this research endeavor.;The research methodology involved an in-depth study of the assembly process with a primary focus on the T-shaped interposer assembly. Good print definition was achieved by determining the printing parameters required for the solder bumping process. This was validated by comparing the experimental results of the solder paste volume with the values obtained from a theoretical model. Component placement guidelines were established by recommending a preferred sequence for placing the components in order to avoid defects and material wastage. Finally, the reflow profile recipe was designed in addition to evaluating different SMT fixture designs in order to reduce warpage in the interposer PCB. Interposer PCB warpage that was within the acceptable limits was achieved by using a particular reflow profile recipe and SMT fixture design. Moreover, recommendations were made to change the interposer PCB panel structure to make the PCB less prone to warpage.;The second part of the research methodology focused on the thermal performance characterization of the STEP assembly. Initially, a baseline performance was evaluated for a single module placed in a server environment with an airflow of 1 m/s. The results were validated with a simulation model developed in FloTHERMRTM. It was shown that the maximum case temperature remains well below the maximum rated case temperature for all BGA devices present on the module. The simulation model was extended further to study four modules placed in parallel, 10 mm apart. The airflow was varied from 0 m/s to 4 m/s. The results showed that a minimum of 1 m/s airflow is necessary to retain good thermal performance. (Abstract shortened by ProQuest.). |
