A high performance parallel architecture for adaptive beamforming

The objective of this dissertation is to implement a special purpose architecture for the enhanced direction-of-arrival system (adaptive beamforming). This research consists of two parts: the development of a new method for adaptive beamforming and the implementation of the new method on a high performance parallel architecture.; First, we propose a modified eigenvector method (MEVM) to enhance the resolution for direction-of-arrival (DOA) estimation. MEVM uses the weighted forward-backward covariance matrix to improve the estimation of the covariance matrix. This dissertation analyzes the effect of using the weighted forward-backward covariance matrix on the performance of the eigenvector method (EVM). We compare the conventional covariance matrix method (EVM) and the weighted forward-backward covariance matrix method (MEVM). The simulation results show that MEVM is more accurate and has better resolution than the conventional EVM under the same noise conditions.; Second, we have conceptually designed a high performance architecture for the implementation of MEVM. In the architecture, several modules cooperate in a pipelined manner. However, one of the modules is very computationally intensive because the eigenvalues and the corresponding eigenvectors of the forward-backward covariance matrix have to be computed. This may be the bottleneck of the system. We investigate the use of the Block Data Parallel Architecture (BDPA) to avoid this bottleneck.; The BDPA is a parallel architecture that achieves high system throughput and high system efficiency. The architecture uses a globally asynchronous and locally synchronous clock distribution scheme to avoid the clock skew problem which may occur in a large synchronous system. The control of the interconnection network is simple and easy to implement because the data transfers between processors are local and uni-directional. The architecture is flexible in the sense that the same number of processors can be used to solve a complex set of problems whose input matrix size may vary.; We have simulated the architecture with a programmable simulator using the timing characteristics of the TMS320C40 digital signal processor. The simulation results consistently show that the parallel architecture can provide high performance, high efficiency, and almost linear speedup for adaptive beamforming.