Thin dielectric technology and memory devices

With advances in technology and scaling, silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based VLSI circuits have remained dominant in data processing and memory applications. Perpetuated by the demand for high-performance and low-cost integrated circuits, the lateral dimensions of the MOSFETs are being aggressively scaled. This in turn demands scaling of the gate oxide thickness as well. Thin gate oxides present both challenges to the modeling and design device of the classical MOSFET and opportunities to explore new device designs and applications.; This study investigates the effect of inversion layer quantization on the capacitance and current characteristics of thin-gate-oxide MOS transistors. In addition, this study explores the possibility of employing thin tunnel oxide for new quasi-nonvolatile memory devices. The performance limitation of a thin dielectric floating gate memory device as well as its potential for dynamic memory applications are discussed. An alternative device structure (i.e. charge-trap based memory cells) is examined by the single charge tunneling model governed by Coulomb Blockade theory.; Two methods of forming charge storage nodes embedded in the gate dielectric are investigated. The resulting devices are then characterized. The first proposed device contains a charge trapping layer of silicon rich oxide (SRO) for dynamic/non-volatile memory application. This device has a similar structure as a MONOS device with SRO instead of silicon nitride for charge trapping on top of a very thin tunneling oxide (<2nm). Since it uses charge trapped in the oxide to create threshold voltage shift, the SRO memory cell is a non-destructive-read device. A new process of depositing SRO and high temperature oxide (HTO) in a single furnace step is developed to better top the control oxide thickness and improve data retention. This device achieved write and erase speeds comparable to that of a DRAM cell and longer data retention time than DRAM. In addition, it can be easily embedded into a CMOS process for low-power dynamic or quasi-nonvolatile memory applications.; Another method of embedding charge storage nodes into the gate dielectric employs germanium nano-crystals formed by oxidation of Si1-xGex . The device consists of a MOSFET with Ge nano-crystals embedded within the gate dielectric. This trap-formation method provides for precise control of the thicknesses of the oxide layers which sandwich the charge-traps, via thermal oxidation. Memory devices with write/erase speed/voltage and retention time superior to previously reported nano-crystal memory devices are demonstrated.; A novel method of growing multiple gate oxide thicknesses below 5nm using oxygen implantation is presented. Experimental results show that multiple thicknesses of gate oxide with differences of up to 20A can be achieved on the same wafer without de gradation of the oxide interface and bulk properties. Unlike oxides grown with nitrogen implantation, oxides fabricated by the proposed method exhibit comparable reliability to that of thermally grown oxides.