Dynamic fault modeling, physical software design concepts, and IC object recognition

Issues surrounding integrated circuit (IC) testing and those of testing large software systems have striking similarities. For large systems in either domain, design for testability (DFT) is key. The single-stuck-at fault model in common use is widely believed to catch many of other kinds of faults. We present an efficient algorithm for generating minimal-length address-sequences for the detection of transition faults in semiconductor read-only memories (ROMs); experimental results demonstrate the inadequacy of the single-stuck-at fault model. We then describe a general, distributable, fault model for zero-delay, gate-level sequential circuit simulation, based on finite state machines (FSMs) described as flow tables; we show how this new model detects "weak" and "leaky" transistors in arbitrary gate-level circuits. Levelization of gates in a circuit simulation can be applied to physical modules in software. We show that a software system implemented as an acyclic graph of atomic primitive modules called components will be testable hierarchically without having to pay for extra "on-chip circuitry" nor render the encapsulation transparent. Treating the component as the fundamental unit of design, we described how to readily infer potential physical dependencies among components directly from the high-level logical relationships (e.g., IsA and Uses) among the logical entities (e.g., classes and functions) these components contain. We describe an important new metric Cumulative Component Dependency (CCD) for characterizing the maintainability and reusability of a software system based on its component dependency graph. We provide a suite of effective new techniques for reducing compile- and especially link-time dependencies among components. Finally the ability to recognize polygon-based IC layout as a collection of objects representing circuit elements connected by path-based wires, enables existing designs implemented using an older fabrication process to be reimplanted quickly in a new process. We describe in detail a novel solution to this complex problem, and present its successful implementation as proof of the efficacy of sound physical design practices in large software systems.