Retargetable compilation for variable-grain data-parallel execution in image processing

This research provides compilation methods that take a single high-level source and (1) target it for data-parallel execution on a wide range of processor granularities from a single processor to a massively parallel array, including (2) subword-level parallelism at each level of granularity as well as (3) the ability to integrate random-access expression into the specification. A retargeting compiler was developed using the methods introduced in this dissertation, and performance measurements were made using a suite of image-processing applications. To show that the same high-level source can be retargeted to widely different architectures with varying granularity, performance comparisons were made from simulation results using both a data-parallel array target architecture and a general-purpose processor target architecture. These validation experiments yield three main results. First, they demonstrate the ability to retarget the same PPE-independent specification to processors of varying grain sizes—ranging from sequential processors (PPE equal to image size) to massively data-parallel multiprocessor systems (PPE equal to one)—with little loss of execution time efficiency or quality of code generated, compared with PPE-dependent source programs. Second, for single and multiprocessor targets with SIMD instruction set extensions, the research compiler code produced speedups linear with subword count on targets with various word widths (for configurations with a PPE ratio relatively larger than the wide word size). Third, the use of hybrid algorithms provided comparable performance to applications written using architecture-dependent source code, which would not be otherwise possible using architecture-independent source code.