| WCDMA (Wideband Code Division Multiple Access) is a third-generation (3G) mobile wireless technology offering much higher data speeds to mobile and portable wireless devices than commonly offered in today's market. The work presented in this dissertation explores design challenges in the front-end receiver circuits in WCDMA. Specifically, this dissertation addresses issues on receiver architectures for a high level of integration, and design and implementation issues for a low-power image rejection architecture that realizes a high image rejection function. The receiver architectures that make high integration possible are the direct conversion and low-IF architectures. However, the direct conversion architecture suffers from a DC offset problem, l/f noise, and second-order distortion issues. Still, most of the published works for WCDMA shy away from the low-IF architecture because of its high image suppression requirements. This dissertation explores techniques that can achieve the desired level of image rejection reliably over the desired bandwidth. The robust high image rejection capability achieved in this work enables the use of a low-IF receiver architecture that meets the WCDMA specifications.;The proposed image rejection down-converter was fabricated using a 0.13mum single poly, 6 layers of metal, digital CMOS (Complementary Metal-Oxide-Semiconductor) process with a 1.8V power supply. The overall chip area is 3200mum x 2800mum; the actual circuits occupy 4.1mm2. The power consumption for the image rejection down-converter is 23.4mW. The average measured image rejection for 10 chips is 46.6dBc over the entire WCDMA bandwidth with 10.8dB noise figure and -7dBm of in-band IIP3. |
