| The rapid growth in demand for high-performance computing and communication systems is driving the need for minimizing power dissipation, integrating higher functionality, increasing throughput, extending operational life, and improving reliability. The ability to scale feature sizes in semiconductor technology enables tremendous advances in building computationally complex VLSI systems at an affordable cost. However, with semiconductor technology being scaled into the deep submicron (DSM) regime, DSM noise consisting of ground bounce, crosstalk, leakage, process variations, etc., has become the primary cause of a reliability problem that challenges the very foundation of the cost and performance benefits of very large scale integration.; In this dissertation, we demonstrate that the energy-efficiencies of present-day integrated circuits are at least an order of magnitude away from the lower bounds, and that noise-tolerance is a practical method of approaching these bounds. We propose design techniques based on noise-tolerance where reliability and energy-efficiency are addressed in a cohesive manner to push the limits of energy reduction. In particular, we develop energy-efficient, noise-tolerant circuit techniques to ensure reliable operation of DSP and communication systems in the presence of DSM noise. We also propose energy-optimum algorithmic noise-tolerant (ANT) techniques to combat DSM noise-like errors induced by aggressive low-power design practices. ANT techniques allow us to achieve substantial energy savings beyond that achievable in conventional design without incurring loss in algorithmic performance.; We develop the soft-decision channel (SDC) model for deriving the lower bounds on energy dissipation of noisy digital systems. We compare the energy-efficiency bounds for domino and noise-tolerant dynamic circuits, and demonstrate that noise-tolerant techniques improve the energy-efficiency when operating at the lower bound. Furthermore, we show that the gap between the lower bounds and the actual energy dissipation is reduced significantly via noise-tolerance. We propose the metric of average noise threshold energy (ANTE) to quantify the noise-immunity and propose an energy-efficient, noise-tolerant dynamic circuit technique referred to as the mirror technique. Simulation results in a 0.35-μm CMOS technology are provided in comparison to static and domino circuits. A MAC ASIC design is presented along with the measured results. We investigate the reliability degradation due to leakage in two ∼0.1-μm CMOS technologies. Two performance metrics, unity noise gain (UNG) and four-stage delay, are proposed to quantify the noise-immunity and speed, respectively. We also propose an energy-efficient, noise-tolerant circuit technique, the boosted-source (BS) technique, for wide fan-in OR gates. We propose the adaptive error-cancellation (AEC) as a practical ANT technique suitable for low-power broadband signal processing. An energy-optimum AEC design strategy is proposed and extended to the design of multi-input, multi-output (MIMO) communication systems. Simulation results of a Gigabit Ethernet 1000Base-T transceiver are evaluated. |
