Electrothermal simulation and temperature-sensitive reliability diagnosis for CMOS VLSI circuits

Over the years, state-of-the-art technologies have continued to push the ULSI chip to higher clock speed and packing density. The speed requirement causes large power consumption and the packing density requirement results in large power density (power per unit area). One direct impact of the increasing power density is the dramatic on-chip temperature rise. For a chip under normal operating conditions, the temperature rise can be as much as a few tens of degrees above the ambience. Without good thermal engineering, significantly nonuniform temperature distribution can lead to a considerable on-chip temperature gradient. The temperature rise and temperature gradient have strong effects on both chip performance and reliability. Therefore, temperature effects must be taken into consideration for performance and reliability analyses.; The goal of the work presented in this dissertation is to develop an electrothermal simulation methodology for temperature-profile estimation, hot-spot identification, and circuit reliability prediction for CMOS VLSI chips. This methodology has been implemented in a CAD tool, ILLIADS-T. ILLIADS-T follows a decoupled electrical/thermal simulation flow which has been proven to be very efficient. A temperature-dependent MOS device modeling technique has been developed. This technique accurately models the device mobility at a wide range of temperatures and couples it into a regionwise-quadratic MOS device model. To calculate the on-chip temperature profile, a chip-level thermal simulation framework has been developed. This framework supports three different thermal simulation techniques which are designed to identify on-chip hot spots, pinpoint the hot-spot temperatures, and profile the full-chip steady-state temperature. A heat-transfer macromodel for the packaging structure is also proposed for the accurate and efficient thermal simulation of package and heat sink. In order to verify the ILLIADS-T simulation results, a tester chip has been designed and fabricated. Very good agreement between simulation and experiment is observed.; ILLIADS-T has been successfully applied to the electromigration (EM) reliability diagnosis and timing analysis. By considering both transistor and interconnect temperatures, the temperature-sensitive EM-induced mean time-to-failure and critical path timing are estimated and discussed.