Power estimation for combinational logic and low-power design | | Posted on:2002-04-11 | Degree:Ph.D | Type:Dissertation | | University:The University of Texas at Austin | Candidate:Kim, Dongho | Full Text:PDF | | GTID:1462390011990767 | Subject:Engineering | | Abstract/Summary: | PDF Full Text Request | | A robust signal transition density propagation method for a zero delay model is presented to obtain the signal transition density for estimating power consumption. The power estimation for the zero delay model is a proper criterion for the determination of the lower boundary of power consumption. Two important estimation methodologies had previously been proposed. While one method has some problems with accuracy because of ignoring simultaneous signal effects, the other method shows some unstable results being caused by introducing the normalized signal transition density. Hence, this research will explore a methodology to achieve robustness and accuracy in signal transition density estimation by taking the input-output transition behavior into account. This work will present a signal transition density estimation method by eliminating the redundancy that is induced by neglecting simultaneous signal effects. In experiments, the proposed methodology shows better robustness, comparable accuracy and elapsed time compared to conventional methods.; Spatial correlation should be treated for estimation accuracy, since some inaccuracy is caused by reconvergent paths. The reconvergent path should be taken into account to apply the signal transition density estimation in real circuits. In general, there are two main stages: i.e. circuit partitioning and computation of signal probability by taking reconvergent paths into account. In this work, a simple circuit partitioning algorithm is proposed by considering the variable search span and the polynomial parameter upgrade method for handling the reconvergent path. In experiments, the search span is effective when the span length is 2.; In the computer arithmetic area, the adder is one of the most important and basic circuit components. Among the various kinds of adders, CLA (Carry Lookahead Adder) is generally considered the fastest and most complex. The complexity is closely related to power consumption, and more complex circuits may require more power consumption. This work will explore the relationship between the generation signal and the propagation signal of the CLA, and will present a low power consumption CLA by taking advantage of the conditional don't care that exists in the generation and propagation signals. The results show that this proposed CLA can reduce switching activity by 9–11% compared to a conventional CLA. | | Keywords/Search Tags: | Signal, Power, Estimation, CLA, Propagation, Method, Proposed | PDF Full Text Request | Related items |
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