Monolithic smart sensor systems based on lead zirconate titanate thin films

This work describes the development of monolithic smart sensor systems by integration of surface-micromachining and piezoelectric thin film technologies with a conventional CMOS fabrication process. By integrating the components of a typical data acquisition or control system on a common silicon substrate it is possible to improve performance, reduce overall processing and assembly costs, and miniaturize conventional systems. The monolithic fabrication sequence utilizes conventional IC processing techniques and is built around an n-well mixed analog/digital CMOS process with two layers of polysilicon and two levels of metallization. By combining common processing steps, the piezoelectric and surface-micromachining capabilities add only four lithography steps to the eleven-mask CMOS process. Low-voltage PMOS transistors fabricated in this process were characterized by threshold voltages of 0.5 V and transconductance parameters of 57 {dollar}mu{dollar}A/V{dollar}sp2.{dollar} Low-voltage PMOS transistors fabricated in this process have threshold voltages of {dollar}-{dollar}0.7 V and 20 {dollar}mu{dollar}A/V{dollar}sp2{dollar} transconductances. A high voltage NMOS transistor was also integrated into the process to buffer low-voltage CMOS signal processing electronics from micromachined electrostatic or piezoelectric actuator loads. High voltage NMOS transistors occupying approximately.0015 cm{dollar}sp2{dollar} sustained a minimum of 100 V drain voltage at 1.2 W. These transistor parameters were not degraded by integration with the monolithic sensors and actuators. The maximum measured unamplified sensitivity of piezoelectric pressure sensors was 245 {dollar}mu{dollar}V/{dollar}mu{dollar}bar for a circular device with 200 {dollar}mu{dollar}m diameter. Analog constant-voltage-gain and general-purpose operational amplifiers were also fabricated in the integrated process. Constant-gain amplifiers based on cascaded operational transconductance amplifiers exhibited a constant gain of 66 dB over a 40 kHz bandwidth. Input capacitance of the amplifier was less than 1 pF while maintaining a maximum input-referred noise level of 4 {dollar}rmmu Vsb{lcub}p-p{rcub}.{dollar} As an indicator of digital circuit performance, 21-stage buffered CMOS ring oscillators were fabricated and tested, showing an average digital gate delay of 3 nsec. The only performance compromise in CMOS electronics was an increased PMOS drain/source contact resistance due to additional thermal processing required by the microstructures. The minimal degradation of CMOS performance confirms the compatibility of surface-micromachining and piezoelectric thin film technologies with standard IC processing.