| Copper has been acknowledged as the interconnect material for future generations of ICs to overcome the bottlenecks on speed and reliability present with the current Al based wiring. A new set of challenges brought to the forefront when copper replaces aluminum, have to be met and resolved to make it a viable option. Unit step processes related to copper technology have been under development for the last few years. In this work, the application of copper as the interconnect material in multilevel structures with SiO{dollar}sb2{dollar} as the interlevel dielectric has been explored, with emphasis on integration issues and complete process realization.; Interconnect definition was achieved by the Dual Damascene approach using chemical mechanical polishing of oxide and copper. The choice of materials used as adhesion promoter/diffusion barrier included Ti, Ta and CVD TiN. Two different polish chemistries (NH{dollar}sb4{dollar}OH or HNO{dollar}sb3{dollar} based) were used to form the interconnects. The diffusion barrier was removed during polishing (in the case of TiN) or by a post CMP etch (as with Ti or Ta). Copper surface passivation was performed using boron implantation and PECVD nitride encapsulation. The interlevel dielectric way composed of a multilayer stack of PECVD SiO{dollar}sb2{dollar} and Si{dollar}sb{lcub}x{rcub}{dollar}N{dollar}sb{lcub}y{rcub}.{dollar} A baseline process sequence which ensured the mechanical and thermal compatibility of the different unit steps was first created. A comprehensive test vehicle was designed and test structures were fabricated using the process flow developed. Suitable modifications were subsequently introduced in the sequence as and when processing problems were encountered.; Electrical characterization was performed on the fabricated devices, interconnects, contacts and vias. The structures were subjected to thermal stressing to assess their stability and performance. The measurement of interconnect sheet resistances revealed lower copper loss due to dishing on samples polished using HNO{dollar}sb3{dollar} based slurry. Interconnect resistances remained stable upto 400{dollar}spcirc{dollar}C, 500{dollar}spcirc{dollar}C and 600{dollar}spcirc{dollar}C for Ti, TiN and Ta barriers respectively. Via resistivity on the order of 10{dollar}sp{lcub}-9{rcub} Omega{dollar}cm{dollar}sp2{dollar} was measured for Cu/Ta/Cu interfaces and no degradation in the via resistance was observed upto 600{dollar}spcirc{dollar}C on the 2 {dollar}mu{dollar}m and 3 {dollar}mu{dollar}m wide contact windows. Characterization of diode leakage and subthreshold currents of CMOS transistors fabricated with Ta adhesion layers, showed the failure of the Ta barrier at 450{dollar}spcirc{dollar}C. Despite the good barrier performance of the CVD TiN films, obtaining low contact resistivity may be a concern.; The potential use of Cu-Mg alloy as the backend metallization has also been studied. Fully encapsulated wiring has been fabricated by causing the Mg to out-diffuse towards the Cu/SiO{dollar}sb2{dollar} interfaces and the free copper surface. The inter-connects exhibited good stability and oxidation resistance, but via resistances were extremely high, probably due to the presence of insulating films like MgO or MgF{dollar}sb2{dollar} at the interface between the two metal levels. It may be possible to decrease the via resistance to values comparable to Cu/Ta/Cu by altering the process flow and using a suitable via clean. When used at the contact level, undesirable interaction with the CoSi{dollar}sb2{dollar} film was observed at temperatures as low as 350{dollar}spcirc{dollar}C. Another problem was the high contact resistance at the Cu-Mg/CoSi{dollar}sb2{dollar} interface. Hence the use of this alloy as a contact fill material is not feasible at this time. An additional barrier layer may be required between the Cu-Mg and CoSi{dollar}sb2{dollar} films to protect the integrity of the silicid... |
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