| Theoretical yield models for area array solder interconnect are proposed and the experimental verification of the models are demonstrated. It is found that an area array solder interconnect can be successfully achieved through three sequential steps: ‘horizontal contact’, in which the solder bumps and their corresponding substrate pads are aligned, ‘vertical contact’, in which the chip collapses toward an equilibrium state as the eutectic solder bumps melt at the melting temperature and all molten solder bumps make contact with their associated substrate pads during the reflow process, and ‘wetting’ in which the molten solder bumps wet the substrate pads. A horizontal contact yield defined by the probability of successful horizontal contact is theoretically modeled as a function of the random parameters such as solder bump size, solder mask thickness and opening size, solder mask definition, solder mask misregistration, translational and rotational placement errors, substrate pattern stretch, etc. In addition, a vertical contact yield defined by the probability of successful vertical contact is theoretically modeled as a function of the random parameters such as solder bump size, chip pad size, substrate pad size, the number of solder joints, substrate warpage, solder mask thickness and opening size, etc. A series of experiments were performed with specially designed flip chips and substrates to verify the models. The experimental results showed good agreements with the prediction of the models. Based on the verified models, design guidelines including process windows and closed form design rules to obtain high interconnect yields are suggested. In particular, tolerable limits of design and process parameters such as bond pad, solder ball size, solder ball pitch, solder mask thickness and opening size, substrate warpage, substrate pattern stretch, solder mask misregistration, placement error, etc. are suggested to statistically achieve interconnect yield defect rate as close to zero as possible. |
