Complementary silicide thin-body silicon-on-insulator CMOS devices

The thin-body silicon on insulator (SOI) transistor is a promising design for the 10–50nm gate length regime. One of its major challenges is the large series resistance of the thin SOI layer. In this work a new thin-body device structure is presented that reduces this resistance by fabricating the source/drain regions out of two low-barrier silicides, one for NMOS and one for PMOS. This device is fabricated with gate lengths as small as 15nm using aggressive electron beam lithography techniques, to demonstrate its immunity to short channel effects. The two complementary silicides used are: PtSi for PMOS, and ErSi_1.7 for NMOS. The devices are fabricated without any doping in the source, drain, or body. A secondary structure is also proposed; adding doped extension regions to the complementary silicide source/drains decreases the influence of the Schottky barrier on current transport. This doped complementary silicide source/drain thin-body structure functions in a manner that is similar to conventional thin-body transistor.; The fabrication of the undoped structure is described in detail, in particular the silicide formation and the electron beam lithography steps. Electrical results for both NMOS and PMOS devices are presented with functional devices down to 15nm gate-length. A transmission model is used to fit the experimental data and to extract the silicide barrier height. This model is also used to examine the influence of oxide thickness scaling and extension doping on expected device performance.; A 2d device simulator, Fielday2d, is used to examine the design space of the thin-body complementary silicide source/drain devices. The doped and undoped designs are compared and the influence of the relevant structure parameters is studied. Simulations suggest that a fully depleted source complementary silicide thin-body structure may exhibit the lower leakage current of the undoped structure and the higher on current of the doped structure.