IPU/LTB: A method for reducing effective memory latency

A method of instruction prefetching independent from branch-based control flow was proposed. Additionally, a method of stride-based data prefetching independent from branch-based lookahead was also proposed, as well as a compiler algorithm for generating desirable loop iteration distances for the data prefetching unit. Data were collected via experimentation of a standard set of benchmarks on a machine-level simulator. Results indicated a significant improvement in these methods of prefetching over branch-based instruction prefetching and branch-based lookahead data prefetching at a reasonable cost in terms of hardware complexity. Trends revealed that greater cache demand yields greater relative improvement by these methods, and that these methods scale well against an increasing processor-to-memory speed ratio.