| Programmable network processing systems play an important and growing role in computing and communications. This dissertation examines the design and analysis of such systems insofar as they intersect in the disciplines of computer architecture and networking.; We first present a quantitative evaluation of the efficacy of a selection of high performance computer architectures when used to implement networking workloads. As a result of the abundance of packet-level parallelism available between packets and between flows of packets, we show that processor architectures that exploit thread-level parallelism exhibit high, scalable performance while those that exploit instruction-level parallelism alone do not. Within this context, both simultaneous multithreading (SNIT) and chip-multiprocessing (CMP) are shown to be effective.; Second, in response to the complexity of networking systems and the large design spaces that must be considered, we describe and evaluate a hybrid modeling framework for network processing systems. Modeling accuracy is validated against the performance of a set of real systems executing the same programs under the same traffic conditions; the models are found to be accurate to around 10% for all tested applications.; Finally, we investigate the role of real-time requirements in networking systems built with network processors. Specifically, we consider the problem of forming worst-case performance bounds for programs running on a commercial multithreaded network processor compute engine. We present a quantitative, formal framework for multithreaded performance and employ it in two ways. First, we couple our closed-form analytical performance formulas with the implicit path enumeration technique (IPET) from the real-time systems literature to bound worst-case task throughput for a class of programs characterized by certain control flow structural properties. Second, we introduce an effective loop re-structuring optimization that can significantly improve worst-case performance. |
