| The iterative "Turbo" principle has recently become an essential method in the design of modern digital communication algorithms as it offers a superior performance over conventional decoding methods. As a result, recent third generation wireless communication standards (e.g., 3GPP and UMTS) have adopted iterative codes as the channel coding scheme.; This dissertation regards the hardware design of the iterative decoders at several abstraction levels. A framework that unifies the hardware abstraction levels is developed. The core of this framework is centered on the use of the trellis-time graph to formulate the time scheduling of the Maximum A Posteriori (MAP) algorithm operations. The dissertation proposes novel techniques to partition and cluster the received information symbols into fragments of trellis steps. Accordingly, construction methods of the trellis fragments on a template hardware architecture are studied.; The development framework is automated into a design flow named IIP-MAP. The automation reduces the development time of new hardware architectures from several weeks to several hours. Implementation of the error correcting code of the third generation wireless standard using Field Programmable Gate Array (FPGA) platforms is used as a case study of the IIP-MAP design flow. |
