| The mismatched materials integration of high quality III-V semiconductors on Si can enable certain optoelectronic devices to benefit from the III-V direct-bandgap while utilizing the breadth of Si wafer processing technology and high-speed electronics on a common rugged substrate. However, the lattice-mismatch, thermal-mismatch, polar on non-polar interfaces and chemical heterovalency of conventional III-V materials, such as GaAs, with Si can generate threading dislocations, thermal cracking, and a host of other defects in epitaxial layers that limit device performance. By using compositionally stepgraded Site interlayers, with the 100% Ge surface nearly lattice-matched to GaAs, the 4% lattice-mismatch between Si and GaAs can be accommodated in the Group IV alloy system. This method has produced threading dislocation densities less than 1 x 10 6 cm-2 in the top Ge layer of fully relaxed Ge/SiGe/Si (SiGe) substrates. Utilizing these graded buffers, controlled heteroepitaxy of GaAs onto Ge surfaces is an important stepping-stone in the realization of III-V on Si technology. However, growth challenges including the suppression of anti-phase domain (APD) formation, control of atomic inter-diffusion, and mitigation of the large (∼63%) thermal expansion coefficient mismatch require that the nucleation conditions for GaAs on Site substrates are comprehensively examined.; In this dissertation we report on the structural quality of the GaAs/Ge interface for GaAs nucleation by solid source molecular beam epitaxy (MBE). Through feedback from these characterizations, optimized growth methods are established, demonstrating the ability to grow defect-free epitaxial GaAs films on Ge substrates. We also present data on the electrical activity associated with defects that result if the growth is not fully controlled. In theses studies we exploit a novel use of an electron beam induced current (EBIC) technique to show the electrical activity associated with anti-phase domains and inter-diffusion from regions as small as 100 nm.; Integrating this GaAs MBE nucleation methodology on the Site graded substrates we show that the GaAs stoichiometry and material properties transfer without degradation from the higher threading dislocation density of the Site substrates. In these studies we show that fundamental defects such as; threading dislocation, anti-phase domains, and atomic inter-diffusion are controlled to a level that enables growth of extremely high quality GaAs device layers. Combined with the low TDD enabled by the Site graded buffer, record GaAs/Si minority carrier lifetimes in excess of 10 ns have been achieved. However, other larger scale defects are shown to have a limiting effect on large area device performance. One such morphological surface defect, known as the "bat", is generated during the UHVCVD Site growth. The defect was comprehensively studied and results indicate that the impact on GaAs device performance was due to dislocation clusters in MBE device layers. Comparison analysis with GaAs overgrowth via metal organic chemical vapor deposition (MOCVD) demonstrated this growth method produced fully-operational large-area device structure. A model relating surface growth rates to an incomplete lattice-mismatch relaxation predicts the formation of these clusters. While challenges remain for monolithic III/V optoelectronic integration on Si, it is clear that the demonstration of successful GaAs nucleation on the Site substrate represents a significant milestone on the path to the final goal of truly integrated III-V devices with Si integrated circuits. |
