Compact electronic soma and synapse circuits fabricated using a low temperature approach

Digital circuits using the von Neumann architecture and complementary metal-oxide-semiconductor (CMOS) electronic devices dominate large-scale processing systems today and are extremely efficient at performing well-defined operations. However, these systems are less efficient at tasks which involve processing large amounts of imprecise information originating from the surrounding environment, such as pattern recognition and outcome prediction. The human brain is the best processor of such information sets, and consists of a large number of primitive elements (1010 neurons and 1014 synapses). Neuromorphic systems are a class of circuits that draw inspiration from the extremely parallel architecture of the brain. A major goal is thus to develop neuromorphic circuits using a large-area, low-power, and highly dense approach.;The major focus of this work is the fabrication of a compact circuit which can implement a biologically realistic synaptic learning rule using low-temperature materials. Ambipolar nanocrystalline-silicon (nc-Si) thin-film transistors (TFTs) are selected as basic building blocks of spiking soma circuits. These TFTs are fabricated at the nanoscale using a CMOS-compatible fabrication process at a maximum temperature of 250 °C. High-κ gate dielectrics are incorporated to achieve lower subthreshold swings and threshold voltages. Soma circuits which consist of a few nc-Si TFTs and capacitors are fabricated and shown to display spiking behavior similar to biological neurons. Electronic synapses are fabricated using Au nanoparticle (NP) memory devices based on nc-Si TFTs and TiN/HfO2/TiN memristors. These are then integrated with the soma circuit to achieve an action potential pair-based learning rule, namely spike-timing-dependent plasticity (STDP). The STDP rule is experimentally demonstrated for the first time using simple rectangular voltage pulses alone. The soma circuits are shown to be capable of driving a significant number of synapses in a large-scale implementation. SPICE models are fit to each fabricated device and simulations are performed to verify the operation of the circuits. Finally simple associative learning is demonstrated using simulations and the pair-based STDP learning rule.