CMOS luminescence detection lab-on-chip: Modeling, design, and characterization

Bioluminescence whereby light is emitted as a result of a chemical reaction offers several advantages over other photo-emissive detection methods such as fluorescence, including low background and the utilization of reagents with extended shelf life. Also, since no filters or excitation sources are needed, lab-on-chip integration is considerably easier. Commercial luminescence detection systems today use expensive cooled CCD-based camera setups and require large micro liter volumes of costly reagents due to the high loss in their optical paths.; There is growing need for miniaturized low cost biosensor systems for environmental and biomedical diagnostics. To address this need we have been investigating systems in which the luminescent chemistry is directly coupled to the detector surface. We developed a simulation model for CCD and CMOS imager-based luminescence detection systems. First the photon flux generation process from luminescence probes using ATP-based and luciferase label-based assay kinetics is modeled. An optics simulator is then used to compute the incident photon flux on the imaging plane for a given photon flux and system geometry. Subsequently, the output image is computed using a detailed image sensor model. To validate the model, we developed an experimental CCD-based system that emulates the integrated CMOS-based platform.; We identified a set of applications including nucleic acid, protein and pathogen detection that require 1--1000 assay sites each of size 150 x 150mum2, and have reaction times of 1--30s with a minimum emission rate of 10-6 lux. As off-the-shelf CCD and CMOS imagers cannot satisfy these requirements, we designed and fabricated a detection SoC. The chip comprises an 8 x 16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP and is fabricated in a 0.18mum CMOS process. Detection of photon flux below 10-6 lux at 30s integration time is achieved by directly coupling the target assay to the photodetector sites, the use of low noise circuits, high resolution ADC, on-chip averaging and background subtraction, and correlated multiple sampling.