Frequency stability in distributed latch travelling wave oscillations

This work presents analysis and modelling of phase noise and jitter in travelling wave oscillators based on distributed CMOS latches (DLTWOs). These oscillators are capable of generating GHz rate square waves and distributing them over large integrated circuits with low skew.; The results show that the frequency stability of DLTWOs is comparable to that of well-designed ring oscillators. A time-domain perturbation analysis is presented in which the DLTWO is broken up into a number of stages like a ring oscillator. The time-domain perturbation analysis shows that excess phase is mainly introduced when voltage noise is amplified in the transitioning latches. The time-domain perturbation analysis is verified by impulse sensitivity function (ISF) simulations. Simulation techniques are described and techniques for drastically reducing the number of simulations required to implement the ISF are introduced. It is shown that very accurate results are possible with as few as 41 simulations and that fairly accurate results are possible with as few as three simulations. Simulation results are compared to measured results for the first integrated DLTWO circuits ever produced. Design implications are explored giving designers insight into designing DLTWOs with reduced frequency instability.