| One of the most crucial factors that fuel the needs for low-power VLSI chips is the increased market demand for portable consumer electronics powered by batteries. The craving for smaller, lighter and more durable electronic products indirectly translates to low-power requirements.; This dissertation proposes various circuit techniques for the memory and the clock network, which are among the major power consuming components in many portable DSP applications. First, a general-purpose high-performance low-power register file design is presented. Based on self-resetting postcharge logic, the design provides wide voltage scalability and avoids short-circuit current. Second, we present a sequential access memory design to further optimize power dissipation and performance by replacing decoders with novel sequencers. The sequential access pattern for memory is ubiquitous in many DSP applications such as FIR filtering and FIFOs. Power dissipation required for address sequencing logic, decoders and drivers for address lines are eliminated by exploiting this characteristic. Third, we present an energy-efficient clock generator based on the harmonic resonant circuit technique. Significant power dissipation for a clock network is reduced because most of the charge is recovered by driving the network resonantly. Experimental results are presented for a comparison with conventional clock drivers and various characteristics of the proposed circuit are quantified. Finally, a novel FIR filter design is presented as a case study to show the feasibility of the proposed circuit techniques for a real DSP application. The high-frequency clock signal needed for FIR filter operations is locally generated from a self-resetting memory control signal. In this way, the system clock frequency is reduced to the sample rate. The datapath is designed in the standard ASIC design methodology without any special interfacing logic. |
