Modelisation, realisation et tests d'un systeme a phase asservie, a controle adaptatif et a gamme dynamique elevee (French text)

The design of a phase locked loop (PLL) often implies a compromise between its essential parameters such as: the robustness of the circuit to the external disturbances, the lock time, the precision of the generated signals, etc.; When the bandwidth of the PLL is narrow, the switching time (ST) necessary to the output signal to reach and then to stabilize at the target frequency is rather high.; Previous studies have shown that to reduce the time ST and to obtain a fast locking time it is, generally, necessary to modify the dynamic behavior of the system.; Our work aims at implementing an entirely integrated PLL system having a narrow bandwidth (<300 KHz) but capable of operating over a wide range of frequencies (10--700MHz). Our objective is to develop PLLs that offer a response time shorter than existing solutions. This PLL targets an application where the root-mean-square jitter of the output signal must be below 1% of the input period duration. During the design process, we considered some constraints of operation such as the supply voltage and power consumption.; In a first step, we propose a method of designing a narrow bandwidth PLL system with short locking time. It is based on a continuous adaptation of the fundamental parameters of the feedback control, which provides better performances than if the parameters are fixed (which often impose a compromise of the characteristics in standard architectures). We will present a theoretical analysis of the system behavior and a detailed analysis of its stability. Finally, we will expose the implementation of the system manufactured in standard 0.18 mum CMOS process.; In the second step of this work, we propose a digital-calibration method that offers a high resolution. The main objective of the proposed method is to reduce the output phase noise induced by the oscillator, which harms in a significant way the performances of PLL systems. The calibration circuit was implemented with a 0.18 mum CMOS process. Measured experimental results are presented; they emphasize the noise attenuation produced by the method. These results are definitely better than existing solutions.