Metal-oxide-semiconductor field effect nanostructure spin lattice devices

This dissertation explored and developed technologies for silicon based spin lattice devices. Spin lattices are artificial electron spin systems with a periodic structure having one to a few electrons at each site. They are expected to have various magnetic and even superconducting properties when structured at an optimal scale with a specific number i of electrons. Silicon turns out to be a very good material choice in realizing spin lattices. A metal-oxide-semiconductor field-effect nanostructure (MOSFENS) device, which is closely related to a MOS transistor but with a nanostructured oxide-semiconductor interface, can define the spin lattices potential at the interface and alter the occupation i with the gate electrode potential to change the magnetic phase. The MOSFENS spin lattices engineering challenge addressed in this work has come from the practical difficulty of process integration in modifying a transistor fabrication process to accommodate the interface patterning requirements.;Two distinct design choices for the fabrication sequences that create the nanostructure have been examined. Patterning the silicon surface before the MOS gate stack layers gives a "nanostructure first" process, and patterning the interface after forming the gate stack gives a "nanostructure last process." Both processes take advantage of a nano-LOCOS (nano-local oxidation of silicon) invention developed in this work. The nano-LOCOS process plays a central role in defining a clean, sharp confining potential for the spin lattice electrons.;The MOSFENS process required a basic transistor fabrication process that can accommodate the nanostructures. The process developed for this purpose has a gate stack with a 15 nm polysilicon gate electrode and a 3 nm thermal gate oxide on a p-type silicon substrate. The measured threshold voltage is 0.25 V. Device processes were examined for either isolating the devices with windows in the field oxide or with mesas defined by the etched trenches filled with oxide.;The nanostructrure patterning processes combined electron beam lithography, reactive ion etching and the nano-LOCOS in a nanostructure last fabrication sequence. The electron beam tool produced holes with diameters down to 10 nm and lattice periods down to 50 nm for defining the spin lattices. The dry etching process was able to transfer the pattern into the polysilicon gate material, and the depth was controlled using the measured etching rate. These dimensions are sufficiently small for spin lattices properties to be important at low temperatures.;Upon combining the NMOS and the nanostructure last processes, MOSFENS spin lattice devices were successfully fabricated. The gates are patterned with lattices having a 50 nm period and 20 nm holes, which is the optimal, targeted ratio of 2.5 for superconductivity. The room temperature current-voltage characteristics of these devices show that the lattice nanostructures significantly reduce the average channel mobility, as expected. However, the essentially unchanged threshold voltage indicates the nano-LOCOS process has given a low-defect nanostructure interface. At room temperature, a change in gate potential of approximately of 18 mV changes the lattice electron occupation from nu = 1 to nu = 2. For these devices, the predicted temperature scale for superconductivity is approximately at 9 K.