Regular design fabrics for low cost scaling of integrated circuits

A method for enabling economical scaling for future ICs by the use of regular design to co-develop process and design is discussed. We have made contributions towards creating the framework required for defining the pattern set used for process optimization, process optimization for regular design fabrics, and the analysis of the economic benefit of the prescribed methodology.;We describe the technique used to define a small set of equivalent pattern classes that can be used for process optimization and characterization. We employ a novel methodology for determining a smaller optical interaction range by analyzing the change in aerial image by introducing deviations to the underlying regular fabric. We also introduce the concept of critical patterns based on sensitivity to yield detractors as well as discuss means of classifying patterns into equivalent pattern classes based on printability metrics. We demonstrate process simplification with the use of regular design fabrics. The application of single exposure lithography for the 32nm technology node as well as an simplified OPC solution are both discussed. The economic benefit of such process simplification as well as improved yield is quantified by analyzing the lithography cost per good die metric. The lithography cost per good die metric is then applied to analytically determine the optimum design style for 32nm as well as the optimum lithography solution for the 22nm technology node.