Performance limits of analog to digital conversion in the presence of noise

Analog-to-digital conversion (ADC) is a key component in most electronic systems. Major applications include communications, networking, and high-quality images and video processing. The increasing performance demands of these systems necessitate the design of ever lower power, lower area, higher speed, and higher resolution ADCs. As such, it is important to understand the fundamental limits and tradeoffs involved in the design of ADCs. In this talk we address the theoretical properties and fundamental performance limits of various architectures for analog-to-digital conversion. Viewing ADC architectures as quantization systems, we study the performance of these architecture in the presence of component variations.; Specifically, we study three basic analog to digital conversion architectures. Namely, the first and second order SigmaDelta and the Beta expansion architectures. We study the distortion of each architecture as a function of the number of bits generated by the encoders (bit cost). Each architecture is studied considering three cases of noise sources, i.e., architectures with ideal elements, architectures with imperfect one bit quantizers and architectures with noise sources that can be modeled as additive input noise. We establish bounds on the distortion bit-cost function for each architecture and each noise source. This analysis provides us with quantitative means of comparing the performance of various architectures in the presence of each noise source. Further, we derive general lower bounds on all ADCs for each noise case. These lower bounds serve as benchmarks for comparing the performance of each architecture to the ultimate performance limit in the presence of each noise source. These results would enhance our understanding of the theoretical aspects of analog-to-digital conversion and signal representation in general, as well as guide the design and performance analysis of ADCs.