Low Trade-Off Security Schemes to Detect and Neutralize Malicious Modifications in Nano-CMOS Based Integrated Circuit

Security of Integrated electronics is threatened by the vulnerabilities such as the globalization of the Integrated Circuits (ICs) industry, where a computing chip can be manufactured anywhere in the world. Without trusted foundries, the systems they develop cannot necessarily be expected to perform as specified due to the susceptibility to attack by a malicious adversary. The threats which arise from malicious modifications to the IC based computing hardware, can disable the system, leak information or produce malfunctions and also provide a back door entry to embedded systems like Cyber Physical System (CPS) or can even deny providing service during the execution of critical applications in an Internet of Things (IoT) platform. Even though these modifications can be detected by the changes produced by them on the characteristics of the computing system, their clever design and placement will make it tedious and sometime almost impossible to detect. Therefore there is a need to address these vulnerabilities without solely relying on their detection. So, we propose a method of incorporating security awareness in hardware design which can neutralize as well as improve the de- tection of these HTs on autonomous and real time systems. It is also important that incorporation of security awareness in the hardware design should not tradeoff critical design goals like power and reliability. To reduce this tradeoff, we propose that security techniques can leverage from power and reliability techniques namely Triple Modular Redundancy (TMR) that address reliability and Power Gating using sleep transistors that address power. Without affecting the basic priorities and structure of these meth- ods, we have leveraged them for security. While the proposed TMR based method improves neutralization of HT effect and the proposed power gating based method improves detection of HTs.