Runtime validation for concurrent architectures

With recent advances in silicon process technology and computer architecture research, modern processors are evolving into multi-threaded/multi-core architectures. These emerging concurrent architectures face significant validation challenges that arise from two distinct sources. Implementations of thread-level parallelism (TLP) involve interactions of many system components. The resulting system complexity has made it increasingly difficult to prevent bug escapes during design verification. Second, due to aggressive technology scaling, processor hardware is becoming more vulnerable to aging- and environment-induced hard failures and soft errors in the field. Such errors cannot be eliminated through conventional design verification or limited local hardware protection. Without proper methods to bridge the verification gap and increase hardware reliability, there may be significant cost penalties due to product deployment delays or runtime system errors.;This research presents a runtime validation approach to help address these challenges. Runtime validation offers the capability to handle both escaped design bugs and dynamic errors by performing online detection of functional failures and effecting subsequent recovery. This research studies several representative forms of concurrent architectures and discusses their validation challenges and the corresponding solutions. (1) For single-core multi-threaded architectures, an instruction-level runtime validation methodology is proposed to address specific issues that arise in computation as well as synchronization/communication of multi-threaded execution. (2) For emerging multi-core shared-memory systems, a critical correctness issue is to ensure that the inter-processor communication through shared memory conforms to the memory ordering rules. This research addresses this by showing how to perform effective runtime validation of memory ordering models, based on dynamic construction and checking of a memory ordering constraint graph using efficient hardware support. (3) Transactional memory has been proposed as a promising solution to effectively harness the increasing processing power of future multi-core systems. The results for memory ordering validation are extended to a runtime validation method for hardware transactional memory. This provides a seamless validation framework for systems running both conventional non-transactional code and new transactional applications. Experimental results show that the proposed solutions have low performance penalty, while providing general robustness against both operational and functional errors with relatively small hardware overhead.