Correction strategies to compensate for image placement errors induced during EUVL mask chucking

In extreme ultraviolet lithography (EUVL), meeting the stringent overlay requirements is one of the most difficult challenges. The EUVL mask nonflatness is a major contributor to overlay errors due to the non-telecentric illumination of the mask in the EUVL scanner. At the sub-32-nm half-pitch nodes, where EUVL is expected to be used in production lines, it is crucial to correct for all sources of mask distortion that induce wafer-level image placement (IP) errors. Simplified finite element (FE) and analytical IP error prediction models were developed for this purpose. These simplified models, along with other commercial models, served as e-beam IP correction strategies to minimize overlay errors in an experimental process initiated by SEMATECH (a consortium of semiconductor companies). The registration and overlay data from the exposures conducted on the ASML EUV ADT (an EUVL scanner) were thoroughly analyzed. In addition, full-scale FE and analytical models were developed to overcome some of the limitations of the simplified models. Several correction techniques were evaluated to determine the most suitable correction procedure for IP errors.