VLSI Implementation of a Low Power, High Energy Efficient, Quasi-ML Fixed Complexity Sphere Decoder for MIMO Communication Systems

Multiple-Input Multiple-Output (MIMO) technology plays a revolutionary role in the development of wireless broadband communication systems. Applying multiple antennas at both the transmitter and receiver sides of a wireless channel, the spectral efficiency can be significantly improved without sacrificing extra bandwidth. The exhaustive-search maximum likelihood (ML) algorithm is well known to be the optimal MIMO detection method. However, its complexity increases exponentially as the constellation size or antenna array increases. To address this issue, sphere decoder (SD) has been proposed as an alternative mean to achieve ML bit error rate (BER) with dramatically reduced complexity. Meanwhile, to meet the stringent battery capacity constraint, SD hardware realization must be optimized at all design aspects to ensure a low power, high energy efficient VLSI implementation.;In this research, we will propose a novel MIMO sphere decoding algorithm with power-aware architecture and circuit techniques. To evaluate its effectiveness in energy efficiency, the proposed sphere decoder is implemented in the IBM low-VT, 90-nm, 8 metal layer standard CMOS process. It supports a 4 x 4 antenna array with flexible modulations from BPSK to 16-QAM. At 0.8V and 125°C, the estimated peak throughput exceeds 1.44Gbps with the core area of 1.3 mm2. At room temperature and 0.8V core supply voltage, the measured power is 4.692 mW with 400 Mbps of constant throughput. This VLSI realization achieves 11.73 pJ/bit in energy efficiency which shows a 61% improvement over the other state-of-the-art sphere decoders recently reported in the literature.