| With technologies scaling, interconnect delay and power consumption has become dominant in deep submicron designs. Three-dimensional Integrated Circuits (3D ICs) have recently emerged as a promising means to mitigate these interconnect-related problems. By stacking multiple active device layers with vertical interconnect, 3D technologies offer designers great opportunities meeting performance and power requirements. Compared to traditional 2D design, 3D technologies provide shorter global interconnects, higher performance, less power consumption, higher packing density and smaller footprints, and low cost mixed-technology capabilities. However, 3D ICs pose several challenges before developing into viable commercial product. First, there is no commercial 3D Electrical Design Automation (EDA) tools to support 3D IC design. Second, there is a lack of testing and verification tools and methods to ensure the correct functionality of 3D ICs. Third, design space exploration at the architectural level is essential to take full advantage of 3D integration. Therefore, as fabrication of 3D architecture becomes feasible, it is urgent to develop corresponding 3D EDA tools and 3D testing methodologies for designers to explore 3D ICs design space and evaluate 3D benefits at architectural level.;This work is intended to address EDA, testing, and architectural exploration challenges faced by 3D ICs by exploring five areas. First, the electrical characteristics of Inter-tier Connections is analyzed for 3D ICs. This evaluation is essential for timing analysis and better system design for 3D IC. Second, a 3D ICs design flow based on OpenAccess (OA) platform is presented. Third, we address the scan chain ordering and optimization problem in 3D ICs. Fourth, Test Access Mechanism (TAM) optimization for core-based 3D System-on-chip (SOC) is discussed. Finally, hybrid cache architecture, which combines traditional SRAM and several emerging non-volatile memory technologies, is explored in 2D as well as 3D space. |
