| Three-dimensional (3D) integrated circuits (ICs) aim to further increase integration density beyond Moore's Law, enhance system performance, and reduce interconnect delays. However, 3D technology introduces both advantages and disadvantages in relation to security. Among the disadvantages of 3D is the potential insertion of a Trojan die into the stack between two legitimate dies or on the top or bottom of the stack. Such a die could be used to snoop information traveling between dies, alter the data being communicated, or otherwise interfere with stack operation.;This dissertation explores the use of in-stack circuitry and various testing procedures to detect and locate a Trojan die, which has been maliciously placed between two legitimate dies, through delay analysis even in the presence of process variations. With these methods, a Trojan die between stacked dies can be revealed and located. We present the advantages and the disadvantages for each of the proposed test structures. Then we explore the performance of these techniques if the attacker is able to modify some of the Through Silicon Vias' (TSVs') characteristics or alters the test structure to avoid detection. Our simulation results show that the proposed techniques can detect a Trojan die in a 3D stack, especially when a test structure that incorporates multiple TSVs between two legitimate dies is used. Developing test structures and analysis for detection of extra dies will enhance the security of future 3D systems. |
