A 45nm CMOS temperature sensing interface for crystal frequency temperature compensation

Multi-radio wireless communication systems (3G/4G/GPS) impose stringent requirements (<+1ppm) on crystal reference clock's frequency stability over wide temperature range (>100°C). Traditionally, discrete analog TCXOs are often used for crystal temperature frequency compensation. Recently, integrated DTCXOs that uses on-chip temperature sensing, SigmaDeltaADC and LUT to achieve lower cost and higher accuracy were presented. However, such system's accuracy will be ultimately limited by the proximity-induced temperature gap between the crystal and sensor. Also, the accuracy of the temperature sensing scheme is degraded by the reduced signal dynamic range and increased 1/f noise floor that occurs as the system scales to low voltage nanoscale CMOS. Furthermore, the low latency, low power and high scalability characteristics demanded by real-time frequency control in SOC motivate the exploration of other alternatives to a SigmaDeltaADC based interface.;In this work, we present a temperature sensing interface addresses the above issues by using (1) in-situ crystal temperature sensing to minimize the proximity-induced temperature sensing error; (2) a 500KS/s 12b digital calibrated SAR ADC to ensure lower power consumption and conversion delay; Also, SAR ADC's highly scalable architecture brings case of process migration. (3) SC front-end that combines I/O and native 45nm transistors to simultaneously alleviate the sensor output scaling requirements and maximize the ADC input dynamic range; and (4) chopping to reduce the 1/f noise. As the core of the temperature sensing interface, the SAR ADC must be able to digitize the sensor output with minimum distortion introduced. Factors limiting the accuracy of the ADC include comparator offset, mismatch of MOM capacitor (-8b in 45nm) and 1/f noise. The SAR ADC addresses these issues by performing offset cancellation, mismatch calibration and input chopping, respectively. Fabricated in 45nm digital-LP CMOS, the final ADC achieves a SNDR of 68.6dB and peak ENOB of 11.2b. The mismatch calibration improves the DNL from +3.2 /-1.0LSB to +/-0.5 LSB, and INL from +2.4/-2.1 LSB to 0.3/-0.6LSB.;The proposed interface was further applied in a crystal frequency temperature compensation scheme, in which a LUT maps the digitized temperature readings of ADC to pre-stored frequency control words to correct a programmable XO's temperature dependent frequency drifts. Temperature compensation is tested at 12 points between -10°C and 80°C. An overall frequency stability of <+0.5ppm is achieved.